Attendees:
Scott Little - Freescale
Graham Helwig - ASTC
Achim Bauer
Marq Kole - NXP
Martin O'Leary - Cadence
Geoffrey Coram - Analog Devices
Kevin Cameron
Ken Bakalar - Mentor Graphics
David Miller - Freescale

Update from Scott Little on the current status of the ASVA work going on.

• Add current SVA into AMS is the goal
• Want to extend SVA to allow access to analog events and analog quantities (probes, variables).
• One area of concern is the simulation cycle and how this will fit in.
• Other issue is how these will fit into the existing grammar for Verilog-AMS, although Scott pointed out that the SVA section of the SV grammar is very self contained.

• Achim questioned whether we would be able to have assertions of analog variables. Answer is yes.
• Achim questioned whether those analog variables will be interpolated when queried by the assertion. Answer, based on the existing LRM, if the variable is controlled (assigned) within an analog event, the value is not interpolated - the last assigned value is returned. If it is assigned outside an analog event, yes, the value will be interpolated.

Regarding the SV - Verilog-AMS merge
It would be ideal if we could keep the SV-AMS and SV document the same in terms
of formatting, layout etc.

The easiest way to do this is to work directly from the SV frame source.

Need to follow up with Karen to see if we can get access to the full SV source.

Some people have volunteered to take on their old sections from the LRM 2.3 work:
Marq - Hierarchical (chap 6)
Martin - system task (chap 9), Mixed Signal (chap 7)
Dave - Expressions (chap 4), Analog Beh (chp 5)
Graham - grammar

The idea is we should go through these sections and get a feel of the amount of
change that will be required.
Then early next year we can generate a road map to prioritize and balance the
workload.

-- DavidMiller - 2011-02-01