Subject: Re: Analog memory in VHDL-AMS (Re: Proposal)
From: siep.onneweer@philips.com
Date: Wed Dec 19 2001 - 23:00:53 PST
Hello Yannick,
Just out of curiosity I had a glance at the Preisach model. Surely you
know it much better, but I may help with some hints for the
implementation.
What you really want to do is detect when the current of the magnetic
device changes direction, which can be done with the Q'above attribute.
Q'above forces an ASP at the instant of current reversal. Just store the
values of the quantities of interest in a signal or variable in a process
at those points. It seems to me that you may need to store quite a large
number of corners of the Preisach boundary. Is that correct? Perhaps
that's an important drawback of this model for your application.
You probably also want to integrate the weighting function Mu over the
Preisach plane. According to Gorbet [1] the integration can be replaced by
a simple summation over the corners of the boundary. This removes the
other of your headaches. Gorbet refers to Mayergoyz [2] but I have not
looked that one up.
Have you considered using the Jiles-Atherton model of ferromagnetic
hysteresis instead of the Preisach model? The J-A model has been available
in various simulators for years (e.g. PSPICE, SABER) and should be easy to
implement in VHDL-AMS. It stores only 'local' history by means of
continuous-time state variables for H and M. Last year I built a similar
model for ferroelectric hysteresis to test one of the commercial VHDL-AMS
systems. I must admit I did not get it to work properly but I blame that
on the error control of the simulator. The model itself works fine in our
own simulator Pstar which uses a proprietary language.
By the way, it is quite possible that the static hysteresis losses are
negligible to AC losses (rotational magnetization losses, eddy current
losses). Maybe you don't need to model the static hysteresis at all.
[1] Robert Benjamin Gorbet, Control of Hystereric Systems with Preisach
Representations, PhD thesis, Waterloo, Ontario, Canada 1997.
[2] I.D. Mayergoyz. Mathematical Models of Hysteresis. Springer-Verlag,
New York, 1991.
Best Regards,
Siep Onneweer
Philips Semiconductors
mailto: Siep.Onneweer@philips.com
Yannick HERVE <herve@erm1.u-strasbg.fr>
Sent by: owner-vhdl-ams@eda.org
12/18/2001 09:34 AM
To: Tom Kazmierski <tjk@ecs.soton.ac.uk>
vhdl-ams@eda.org
cc: (bcc: Siep Onneweer/SVL/SC/PHILIPS)
Subject: Re: Analog memory in VHDL-AMS (Re: Proposal)
Classification:
Hi,
My problem is more complex than a comparator.
The problem is the computation of the magnetic state of a material using
the Preisach model.
It is very close to the ising model (spin glass). If this model could be
used it would be
possible to work with the minor cycles of the material and to find the
operation point of a
switching power supply (new generation of mobiles, very low comsumption).
It is possible with the hAMSter violation but I dont have a solution in
respect with the
standard..
For the "static variables" in procedural, I think it is possible to let
values constant
during iterations.This feature could allow static behevioral (?)
I am not specialist of the kernel, and I apologize if I say big mistakes.
Yannick HERVE
Tom Kazmierski wrote:
> Yannick,
> The problem of analog memory in applications with hysteresis
> has been addressed before. You might find the
> following two examples of interest. One is an analog
> Schmitt trigger available from our Validation web site:
> http://www.syssim.ecs.soton.ac.uk/vhdl-ams/examples/ex5.htm
> The other, showing a similar idea, is a comparator with hysteresis
> presented by Ernst Christen and Ken Bakalar in their
> paper "VHDL-AMS - A Hardware Description Language for Analog
> and Mixed Signal Applications", IEEE Trans on CAS, v.46, no 10,
> Oct 1999, pp. 1263-1272
>
> In short, you can have analog memory in signals or variables, as long
> as the variables are 'static', such as process variables. The Schmitt
example
> uses a signal and the comparator one uses a variable in a process.
> I believe shared variables declared on the architecture level
> can also be used.
>
> Eduard's comment reflects well the WG thinking with regards to
procedurals.
> I too would be against your idea of making local variables in
procedurals static (static
> local variables in C are ugly enough :-). For one, a VHDL-AMS model may
use
> more than one instance of the same procedural (eg.,say, many instances
of
> the same transistor model). I reckon 'static' storage in procedurals
would create a mess.
>
> Regards
> Tom Kazmierski
> P1076.1 Chair
>
> --- Department of Electronics and Computer Science,
> --- University of Southampton, Southampton, Hampshire, SO17 1BJ,
> --- UNITED KINGDOM
> --- tjk@ecs.soton.ac.uk tel. +44 2380 593520 fax. +44 2380 592901
> --- http://www.syssim.ecs.soton.ac.uk/
>
> At 17:08 17/12/2001, Yannick HERVE wrote:
> >Hello,
> >
> >I want to submit to you some ideas for the future of the IEEE 1076.1999
> >standard.
> >
> >1/ For now I work on a model who needs memory in the analog "process".
> >It is a Preisach approach aiming at modeling a hysteretic material.
> >I use the hAMSter tool. With it, the procedural statement allows to
keep
> >values of variables between two evaluations. For my work it is very
good
> >(it is the only solution of my problem). By the way, the standard says
> >that the declaration in the procedural will be reinitialized at each
> >avaluation.
> >I think It would be better to let variables in procedural to be static
> >and to keep their values between two evaluations.
> >
> >2/ I am very stucked for a model. I want to schedule a process at each
> >ASP (Analog Simulation Point) in order to monitor the time step.
> >
> >I think it would be good for the model designer to have access from the
> >analog kernel to an implicit signal, ASP, which toggles between true
and
> >false at each ASP.
> >
> >The following instruction would then be valid :
> > wait on ASP;
> >or wait on ASP until A='0';
> >or wait on ASP for 3 ns;
> >
> >Such constructs would offer great possibilities, as a process could
> >actually "see" an ASP.
> >
> >3/ Is it possible to open the syntaxic expession 'dot ?
> >In order to express new class of models it would be very interesting to
> >write
> >Q1'dot(Q2) where Q1 and Q2 are known quantities. When Q2 is not present
> >the derivative is relative to time.
> >
> >With the current syntax the compiler is able to isolate "analog
> >equations" and "logic equations". With this new syntax the compiler
> >would be able to manage "differential equations".
> >It would be up to the simulator to eventually manage this feature.
> >
> >Best regards
> >
> >--
> >Yannick HERVE
-- Yannick HERVE (Il est très zen, hervé)Perso : GSM : 06 75 23 00 19 Tèl : 03 88 74 38 97
Travail : Tél : 03 902 44422 Secr : 03 902 44339 Fax : 03 902 44359
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