Subject: Proposal
From: Ernst Christen (Ernst_Christen@avanticorp.com)
Date: Tue Dec 18 2001 - 10:38:22 PST
Yannick,
Thank you for your ideas for the future direction of IEEE 1076.1. As
already mentioned by several others, all three ideas were considered
and discussed by the Working Group or one of its subcommittees during
either the requirements phase or the language design phase. The first
two were rejected, the third postponed. Here is why.
One of the major requirements for the language was to not specify the
algorithms to be used to simulate a model. The reason for this
requirement is that designers want to trade accuracy for simulation
speed, and vendors have different ways of providing such support.
The approach taken by the Language Design Committee (LDC) to address
this requirement was to define the qualities of the solution rather
than the method to find it. The definitions are such that in the limit
(unlimited precision, unlimited time) the numerical solution would
reach the mathematical solution. An intended consequence of the
definitions is that it is neither possible to count the number of
iterations needed to find an ASP nor to make the model depend on the
interval between ASPs. Your first suggestion would allow counting the
number of iterations, while your second suggestion would make the
solution dependent on the time points selected by the analog solver.
In both cases changing some algorithmic option such as the local
truncation error could yield a different solution, which would have
violated the requirement.
Note that it is possible to use VHDL 1076-1993 shared variables to
retain state across Newton iterations. The result is not defined in
VHDL-1076.1 -- you can expect different results in different
implementations of VHDL-AMS, or even in the same implementation for
different values of tuning parameters.
You state that keeping variable values between evaluations of the
procedural is the only way to solve your problem. I suspect that you
feel this way because of the hysteresis, but I cannot comment without
knowing more about the problem. However, I can say that I have seen
models exhibiting hysteretic behavior implemented in languages
without using the facilities you request. In particular, the LDC
intended an algorithm requiring memory (such as an algorithm
exhibiting hysteresis) to use signals or local variables in processes
(not procedurals!) as memory elements. "Analog" memory was excluded
by design.
Your third suggestion would extend the language to support partial
derivatives. Such support was postponed for two major reasons:
a) the class of algorithms needed to solve PDEs is quite different
from the algorithms used to solve initial value problems described
by DAEs, which is what is currently supported by the language
definition.
b) support for PDEs would also require support for boundary
conditions, which would have added a lot of additional baggage to
the language, in particular semantics for geometry
For these reasons PDE support was postponed till a future release of
the language. Work in this direction has begun in a study group about
RF and microwave extensions to VHDL-AMS, chaired by John Willis
(jwillis@ftlsys.com).
Thanks.
Ernst Christen
Ken Bakalar
> Hello,
>
> I want to submit to you some ideas for the future of the IEEE 1076.1999
> standard.
>
> 1/ For now I work on a model who needs memory in the analog "process".
> It is a Preisach approach aiming at modeling a hysteretic material.
> I use the hAMSter tool. With it, the procedural statement allows to keep
> values of variables between two evaluations. For my work it is very good
> (it is the only solution of my problem). By the way, the standard says
> that the declaration in the procedural will be reinitialized at each
> avaluation.
> I think It would be better to let variables in procedural to be static
> and to keep their values between two evaluations.
>
> 2/ I am very stucked for a model. I want to schedule a process at each
> ASP (Analog Simulation Point) in order to monitor the time step.
>
> I think it would be good for the model designer to have access from the
> analog kernel to an implicit signal, ASP, which toggles between true and
> false at each ASP.
>
> The following instruction would then be valid :
> wait on ASP;
> or wait on ASP until A='0';
> or wait on ASP for 3 ns;
>
> Such constructs would offer great possibilities, as a process could
> actually "see" an ASP.
>
> 3/ Is it possible to open the syntaxic expession 'dot ?
> In order to express new class of models it would be very interesting to
> write
> Q1'dot(Q2) where Q1 and Q2 are known quantities. When Q2 is not present
> the derivative is relative to time.
>
> With the current syntax the compiler is able to isolate "analog
> equations" and "logic equations". With this new syntax the compiler
> would be able to manage "differential equations".
> It would be up to the simulator to eventually manage this feature.
>
> Best regards
>
> --
> Yannick HERVE
Yannick HERVE writes:
> Hello,
>
> I want to submit to you some ideas for the future of the IEEE 1076.1999
> standard.
>
> 1/ For now I work on a model who needs memory in the analog "process".
> It is a Preisach approach aiming at modeling a hysteretic material.
> I use the hAMSter tool. With it, the procedural statement allows to keep
> values of variables between two evaluations. For my work it is very good
> (it is the only solution of my problem). By the way, the standard says
> that the declaration in the procedural will be reinitialized at each
> avaluation.
> I think It would be better to let variables in procedural to be static
> and to keep their values between two evaluations.
>
> 2/ I am very stucked for a model. I want to schedule a process at each
> ASP (Analog Simulation Point) in order to monitor the time step.
>
> I think it would be good for the model designer to have access from the
> analog kernel to an implicit signal, ASP, which toggles between true and
> false at each ASP.
>
> The following instruction would then be valid :
> wait on ASP;
> or wait on ASP until A='0';
> or wait on ASP for 3 ns;
>
> Such constructs would offer great possibilities, as a process could
> actually "see" an ASP.
>
> 3/ Is it possible to open the syntaxic expession 'dot ?
> In order to express new class of models it would be very interesting to
> write
> Q1'dot(Q2) where Q1 and Q2 are known quantities. When Q2 is not present
> the derivative is relative to time.
>
> With the current syntax the compiler is able to isolate "analog
> equations" and "logic equations". With this new syntax the compiler
> would be able to manage "differential equations".
> It would be up to the simulator to eventually manage this feature.
>
> Best regards
>
> --
> Yannick HERVE
>
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