Subject: Analog memory in VHDL-AMS (Re: Proposal)
From: Tom Kazmierski (tjk@ecs.soton.ac.uk)
Date: Tue Dec 18 2001 - 08:18:31 PST
Yannick,
The problem of analog memory in applications with hysteresis
has been addressed before. You might find the
following two examples of interest. One is an analog
Schmitt trigger available from our Validation web site:
http://www.syssim.ecs.soton.ac.uk/vhdl-ams/examples/ex5.htm
The other, showing a similar idea, is a comparator with hysteresis
presented by Ernst Christen and Ken Bakalar in their
paper "VHDL-AMS - A Hardware Description Language for Analog
and Mixed Signal Applications", IEEE Trans on CAS, v.46, no 10,
Oct 1999, pp. 1263-1272
In short, you can have analog memory in signals or variables, as long
as the variables are 'static', such as process variables. The Schmitt example
uses a signal and the comparator one uses a variable in a process.
I believe shared variables declared on the architecture level
can also be used.
Eduard's comment reflects well the WG thinking with regards to procedurals.
I too would be against your idea of making local variables in procedurals static (static
local variables in C are ugly enough :-). For one, a VHDL-AMS model may use
more than one instance of the same procedural (eg.,say, many instances of
the same transistor model). I reckon 'static' storage in procedurals would create a mess.
Regards
Tom Kazmierski
P1076.1 Chair
--- Department of Electronics and Computer Science,
--- University of Southampton, Southampton, Hampshire, SO17 1BJ,
--- UNITED KINGDOM
--- tjk@ecs.soton.ac.uk tel. +44 2380 593520 fax. +44 2380 592901
--- http://www.syssim.ecs.soton.ac.uk/
At 17:08 17/12/2001, Yannick HERVE wrote:
>Hello,
>
>I want to submit to you some ideas for the future of the IEEE 1076.1999
>standard.
>
>1/ For now I work on a model who needs memory in the analog "process".
>It is a Preisach approach aiming at modeling a hysteretic material.
>I use the hAMSter tool. With it, the procedural statement allows to keep
>values of variables between two evaluations. For my work it is very good
>(it is the only solution of my problem). By the way, the standard says
>that the declaration in the procedural will be reinitialized at each
>avaluation.
>I think It would be better to let variables in procedural to be static
>and to keep their values between two evaluations.
>
>2/ I am very stucked for a model. I want to schedule a process at each
>ASP (Analog Simulation Point) in order to monitor the time step.
>
>I think it would be good for the model designer to have access from the
>analog kernel to an implicit signal, ASP, which toggles between true and
>false at each ASP.
>
>The following instruction would then be valid :
> wait on ASP;
>or wait on ASP until A='0';
>or wait on ASP for 3 ns;
>
>Such constructs would offer great possibilities, as a process could
>actually "see" an ASP.
>
>3/ Is it possible to open the syntaxic expession 'dot ?
>In order to express new class of models it would be very interesting to
>write
>Q1'dot(Q2) where Q1 and Q2 are known quantities. When Q2 is not present
>the derivative is relative to time.
>
>With the current syntax the compiler is able to isolate "analog
>equations" and "logic equations". With this new syntax the compiler
>would be able to manage "differential equations".
>It would be up to the simulator to eventually manage this feature.
>
>Best regards
>
>--
>Yannick HERVE
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