Interface Requirements and Relevant Documentation

Requirement List

• Should NOT instantiate hardware: - Question - do people agree with this premise? -- BAH - 2012-11-13
  • VHDL+ provides instantiated interfases:
    • defines an Interface 'between' any number of end types (including 1).
    • Interfaces connect via an 'interface port' list, additional in 'component' and 'entity' declarations (leads on to 'interface map' and 'interface signal' extras).
  • SystemVerilog provides instantiated interfaces:
• An Interface should reference a composite (sub)type:
  • an interface is a bundle of signals.
  • the purpose of the interface is to group these signals together in order to improve connectivity and code comprehension.
• An Interface should provide directional port mode definability for each element of said composite type (records and arrays):
  • an interface needs to be able to define various I/O modes, at its simplest master and slave.
  • an interface should not necessarily be limited to just two I/O mode types.
  • an interface should be able to connect to just one port, e.g. to provide protocol validation/stimulation
• An Interface should provide support for interface protocol testing
• An Interface should not be too complex in syntax, in order to provide simple interfaces, e.g. a record of Std_Logic type elements (reset, clock)

Relevant Email threads:

• vhdl-200x: Requirements for VHDL Interfaces
• vhdl-200x: Requirements for Interfaces
• vhdl-200x: Re: Requirements for Interfaces, Part 1
• vhdl-200x: Re: Requirements for Interfaces, Part 2
• VHDL Interfaces (was RE: EXTERNAL: Re: vhdl-200x: VHDL enhancements wish list)
• vhdl-200x: Directional records proposal
• vhdl-200x: Records with directional subtypes

Relevant Proposals:

• IEEE 200X FT-17 - Jim Lewis - Composite interface mode
• IEEE 200X FT-14 & FT-15 - Ryan Hinton - Arrays of unconstrained arrays and records with unconstrained arrays
• New Requirement - Interfaces / Record IO
• New Requirement - Record Introspection
• New Requirement - Generics on Types
• IR2067 - Martin Trautmann - Enhancement: Logical link interface abstraction - analyzed: Peter Ashenden
• IR2089 - Andreas Doering - Directional records - never analyzed

Relevant Documents:

• Accellera VHDL-TC - Jim Lewis - Interfaces