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---+ Interface Requirements and Relevant Documentation

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---++ Requirement List
   * Should *NOT* instantiate hardware: <span style="color: #ff0000;">- Question -</span> do people agree with this premise? -- [[Main.BrentHahoe][BAH]] - 2012-11-13 
      * VHDL+ provides instantiated interfases: 
         * defines an Interface '<strong>between</strong>' any number of end types (including 1).
         * Interfaces connect via an '<strong>interface port</strong>' list, additional in '<strong>component</strong>' and '<strong>entity</strong>' declarations (leads on to '<strong>interface map</strong>' and '<strong>interface signal</strong>' extras).
      * !SystemVerilog provides instantiated interfaces:
   * An Interface should reference a composite (sub)type: 
      * an interface is a bundle of signals.
      * the purpose of the interface is to group these signals together in order to improve connectivity and code comprehension.
   * An Interface should provide directional port mode definability for each element of said composite type (records and arrays): 
      * an interface needs to be able to define various I/O modes, at its simplest master and slave.
      * an interface should not necessarily be limited to just two I/O mode types.
      * an interface should be able to connect to just one port, e.g. to provide protocol validation/stimulation
   * An Interface should provide support for interface protocol testing
   * An Interface should not be too complex in syntax, in order to provide simple interfaces, e.g. a record of Std_Logic type elements (reset, clock)
---++ Relevant Email threads:

<sticky>
   * [[http://www.eda.org/vhdl-200x/hm/0504.html][vhdl-200x: Requirements for VHDL Interfaces]]
   * [[http://www.eda.org/vhdl-200x/hm/0518.html][vhdl-200x: Requirements for Interfaces]]
   * [[http://www.eda.org/vhdl-200x/hm/0522.html][vhdl-200x: Re: Requirements for Interfaces, Part 1]]
   * [[http://www.eda.org/vhdl-200x/hm/0525.html][vhdl-200x: Re: Requirements for Interfaces, Part 2]]
   * [[http://www.eda.org/vhdl-200x/hm/1296.html][ VHDL Interfaces (was RE: EXTERNAL: Re: vhdl-200x: VHDL enhancements wish list)]]
   * [[http://www.eda.org/vhdl-200x/hm/1677.html][vhdl-200x: Directional records proposal]]
   * [[http://www.eda.org/vhdl-200x/hm/1771.html][vhdl-200x: Records with directional subtypes]]</sticky>

---++ Relevant Proposals:
   * [[http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft17_composite_interface_mode.txt][IEEE 200X FT-17 - Jim Lewis - Composite interface mode]]
   * [[http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft14_composites_with_unconstrained_arrays.pdf][IEEE 200X FT-14 & FT-15 - Ryan Hinton - Arrays of unconstrained arrays and records with unconstrained arrays]]
   * [[http://www.eda.org/twiki/bin/view.cgi/P1076/BlockInterfaces][New Requirement - Interfaces / Record IO]]
   * [[http://www.eda.org/twiki/bin/view.cgi/P1076/RecordIntrospection][New Requirement - Record Introspection]]
   * [[http://www.eda.org/twiki/bin/view.cgi/P1076/GenericTypes][New Requirement - Generics on Types]]
   * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2067.txt][IR2067 - Martin Trautmann - Enhancement: Logical link interface abstraction - analyzed: Peter Ashenden]]
   * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2089.txt][IR2089 - Andreas Doering - Directional records - never analyzed]]

---++ Relevant Documents:
   * [[http://www.eda.org/vasg/docs/Interfaces.pdf][Accellera VHDL-TC - Jim Lewis - Interfaces]]
Topic revision: r14 - 2013-05-14 - 11:00:22 - BrentHahoe
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