We are getting requests from customers requesting a standardized format for the interface to foreign routines. This is something that currently does not exist in the LRM and causes portability problems. I can foresee a solution that makes use of the Direct-C work done in SystemVerilog to provide a relatively low cost interface between the simulator and a routine written in C (or any language that support C compatible calling conventions). Is this something we can add to the work for the next VHDL-AMS? Regards David David W. Smith Synopsys Scientist Synopsys, Inc. Synopsys Technology Park 2025 NW Cornelius Pass Road Hillsboro, OR 97124 Voice: 503.547.6467 Main: 503.547.6000 Cell: 503.560.5389 FAX: 503.547.6906 Email: david.smith@synopsys.com<mailto:david.smith@synopsys.com> http://www.synopsys.com Saber Accelerates Robust Design Predictable. Repeatable. Reliable. Proven. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. To unsubscribe to the vhdl-ams mailing list: mailto:Majordomo@eda.org?subject=Unsubscribe&body=unsubscribe%20vhdl-amsReceived on Tue Sep 25 15:18:59 2012
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