No encryption!

Hallo everybody,

Please excuse a word of warning against encryption: According to my
experience, it serves not to protect your knowledge but your ignorance!
The limitations and shortcomings that any analogue model will always
have are thus not detected and improved by the user, but they will
continue to give inaccurate or even wrong results ... 
We have already experienced that a tool vendor went out of business, and
we could not reuse the improvements to our own models ... 
So when a semiconductur vendor does not want to show his models: Get a
better partner in time!

I suppose I cannot stop anybody encrypting a source file as whole. This
applies to any ASCII language. But this is not what it is about, for the
following reason: It has proven reliable and efficient to generate
documentation out of the model head itself and additional information
tagged in the code and in the comments. So the solution cannot be as
simple as encrypting files, but has to be something in line with the
Cadence slides. (Had VHDL-AMS provided a deeper hierarchy of model
inheritance than entity and arhitecture, it might have been possible to
let the user know the entity and the "coarse architecture" but not the
"fine architecture".)

I also fear that encryption is counter-productive for current attempts
to create a tool-independent open source "meta-language". But as long a
the models themselves are simulator-specific, why not allow individual
schemes?

Best regards,
Thomas

> -----Original Message-----
> From: owner-vhdl-ams@server.eda.org 
> [mailto:owner-vhdl-ams@server.eda.org] On Behalf Of Ernst Christen
> Sent: Monday, April 24, 2006 9:39 PM
> To: Muranyi, Arpad
> Cc: vhdl-ams@server.eda.org
> Subject: Re: Question on encryption
> 
> Hi Arpad,
> 
> Encryption is a topic that comes up from time to time. The 
> issue is not specific to 
> VHDL-AMS, but affects also VHDL (IEEE Std 1076). A proposal 
> has been submitted to the VHDL 
> Analysis and Standardization Group (VASG) to support 
> encryption in a VHDL text. You can 
> find some information about the topic by following the 
> VHDL-200x link under P1076 at 
> eda.org. Go to Old VHDL-FT documents, near the bottom there 
> are links to relevant 
> documents. There is also a presentation at 
> http://www.accellera.org/apps/group_public/download.php/118/VH
> DL_IP_Encryption.ppt.
> 
> Thanks.
> Ernst Christen
> 
> On Mon, 24 Apr 2006 11:25:32 -0700, Muranyi, Arpad wrote:
> > Hello everyone,
> >
> > Sorry for bringing up such off topic questions all the time,
> > but I would like to find out whether encryption has been
> > considered by the workgroup for VHDL-AMS models.
> >
> > The reason I am asking is because this has been brought up
> > in the recent IBIS Open Forum discussions in connection
> > with modeling bleeding edge high speed buffers behaviorally.
> > Semiconductor vendors feel increasingly uneasy about
> > releasing even behavioral models for such buffers without
> > encryption.  In addition we do not like the idea of using
> > the individual and proprietary encryption schemes of EDA
> > vendors, because that would require the model makers to
> > encrypt the same model multiple times for each tool.  It
> > seems that there is a strong need for some sort of a tool
> > independent encryption scheme.
> >
> > We thought we should look around what has been done, if
> > anything, before we reinventing the wheel.
> >
> > Thanks,
> >
> > Arpad
> > =============================================================
> 
>