RE: Unreachable Grammar

Thilo,

The production for declaration serves to formalize what language elements
are declarations. That is important for other parts of the LRM. For example,
in Clause 10, Scope and visibility, semantic rules refer to the occurrence
of declarations within declarative regions. By formally enumerating what is
a declaration, it is clear what the scope and visibility rules refer to.

Hope this clarifies things.

Cheers,

Peter Ashenden
P1076/P1076.1 Technical Editor

--
Dr. Peter J. Ashenden                peter@ashenden.com.au
Ashenden Designs Pty. Ltd.           www.ashenden.com.au
PO Box 640                           VoIP: 0871270078@sip.internode.on.net
Stirling, SA 5152                    Phone (mobile):  +61 414 709 106
Australia

> -----Original Message-----
> From: owner-vhdl-ams@eda.org [mailto:owner-vhdl-ams@eda.org] 
> On Behalf Of Thilo Brause
> Sent: Monday, 13 February 2006 19:20
> To: vhdl-ams@eda.org
> Subject: Unreachable Grammar
> 
> 
> Dear VHDL-AMS Working Group,
> in the VHDL-AMS Syntax is the element
> 
> object_declaration :=
> constant_declaration | signal_declaration | variable_declaration | 
> file_declaration | terminal_declaration | quantity_declaration
> 
> This element can only be reached via the "declaration" element, but 
> there is no way to reach "declaration", if beginning from design_file.
> 
> I read through the description of the IEEE Standard, but there 
> "declaration" was only mentioned on page 50 , and not 
> declared further. 
> I assume, that "declaration" is something like an abstract 
> superclass of 
> all kinds of declarations, but if it is that case, why is 
> "declaration" 
> and "object_declaration" mentioned in the syntax?
> It would be helpful if somebody could clarify the intentions behind 
> these elements.
> Yours Sincerely,
>     Thilo Brause
>