Re: Unreachable Grammar

It's a means for defining a collection of things (i.e., enumerating the members of the 
collection), in this case declarations that are object declarations, for the purpose of 
defining common semantics for the collection.

Ernst Christen

On Mon, 13 Feb 2006 00:50:25 -0800, Thilo Brause wrote:
> Dear VHDL-AMS Working Group,
> in the VHDL-AMS Syntax is the element
>
> object_declaration :=
> constant_declaration | signal_declaration | variable_declaration |
> file_declaration | terminal_declaration | quantity_declaration
>
> This element can only be reached via the "declaration" element, but
> there is no way to reach "declaration", if beginning from design_file.
>
> I read through the description of the IEEE Standard, but there
> "declaration" was only mentioned on page 50 , and not declared further.
> I assume, that "declaration" is something like an abstract superclass of
> all kinds of declarations, but if it is that case, why is "declaration"
> and "object_declaration" mentioned in the syntax?
> It would be helpful if somebody could clarify the intentions behind
> these elements.
> Yours Sincerely,
>     Thilo Brause