-- One entity inside the design where we can do high level programming -----
   entity Example_1 is
        port (AE, BE : in Natural;
              CE : out Natural);
   end Example_1

   architecture Example_1_RTL of Example_1 is
      DE : Natural;
   begin

      DE <= AE + BE;
      CE <= DE * BE;

   end Example_1_RTL;


   -- Entity that interfaces the previous entity to an external one --------
   entity Top is
        port (A, B : in Std_Logic_Vector (7 downto 0);
              C : out Std_Logic_Vector (23 downto 0);
   end Top

   architecture Top_RTL of Top_RTL is
      signal AT, BT, CT : Natural;
   begin

      AT <= To_Integer (Unsigned (A));
      BT <= To_Integer (Unsigned (B));

      Exemple_1_Inst : entity Work.Example_1 port map (AE => AT,
                                                       BE => BT,
                                                       CE => CT);
      C <= Std_Logic_Vector (To_Unsigned (CT, C'Length));
      -- Check if CT overflows C
      assert To_Integer (Unsigned (C)) = CT severity Failure;

   end Top_RTL;