AmsExamplesDCM < VerilogAMS

VerilogAMS Web>AmsExamples>AmsExamplesDCM (2012-09-14, DavidMiller) (raw view)EditAttach

---+ Digital Component Models (DCM)
| *Type* | *Description* | *Source* |
| [[#AND][Logic AND]] | 'and' module with variable number of input terminals | [[%ATTACHURL%/and.va][and.va]] |
| [[#NAND][Logic NAND]] | 'nand' module with variable number of input terminals | [[%ATTACHURL%/nand.va][nand.va]] |
| [[#OR][Logic OR]] | 'or' module with variable number of input terminals | [[%ATTACHURL%/or.va][or.va]] |
| [[#NOR][Logic NOR]] | 'nor' module with variable number of input terminals | [[%ATTACHURL%/nor.va][nor.va]] |
| [[#XOR][Logic XOR]] | 'xor' module with variable number of input terminals | [[%ATTACHURL%/xor.va][xor.va]] |
| [[#XNOR][Logic XNOR]] | 'xnor' module with variable number of input terminals | [[%ATTACHURL%/xnor.va][xnor.va]] |
| [[#NOT][Logic NOT]] | Inverter module with variable number of input and output terminals | [[%ATTACHURL%/not.va][not.va]] |
| [[#DFF][D-Flip Flop]] | D-Flip Flop | [[%ATTACHURL%/d_ff.va][d_ff.va]] |
| [[#JKFF][JK-Flip Flop]] | JK-Flip Flop | [[%ATTACHURL%/jk_ff.va][jk_ff.va]] |
| [[#RSFF][RS-Flip Flop]] | RS-Flip Flop | [[%ATTACHURL%/rs_ff.va][rs_ff.va]] |
| [[#TFF][T-Flip Flop]] | T-Flip Flop | [[%ATTACHURL%/t_ff.va][t_ff.va]] |
| [[#ClkGen][Clock Generator]] | Clock generator for symmetric clock | [[%ATTACHURL%/clock_generator.va][clock_generator.va]] |
| [[#BER][Bit Error Rate]] | Bit error rate calculator model | [[%ATTACHURL%/biterrorrate.va][biterrorrate.va]] |
---++ <a name="AND">Logic AND</a>
| *Module Name* | V_and |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="NAND">Logic NAND</a>
| *Module Name* | V_nand |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="OR">Logic OR</a>
| *Module Name* | V_or |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="NOR">Logic NOR</a>
| *Module Name* | V_nor |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="XOR">Logic XOR</a>
| *Module Name* | V_xor |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="XNOR">Logic XNOR</a>
| *Module Name* | V_xnor |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="NOT">Logic NOT</a>
| *Module Name* | V_not |
| *Terminals* | in: terminal : input [0:size-1] voltage<br /> out: terminal : output [0:size-1] voltage |
| *Parameter* | size: number of input bits = 2 from [2:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> tdelay: time between change on a input and output : 5n from [0:inf)<br /> trise: rising time = 1n from [0:inf)<br /> tfall: falling time = 1n from [0:inf) |
---++ <a name="DFF">D-Flip Flop</a>
| *Module Name* | V_d_ff |
| *Terminals* | q: logic output : output voltage<br /> qbar: inverse logic output : output voltage<br /> clk: clock terminal : input voltage<br /> d: data input : input voltage |
| *Parameter* | tdelay: time between change on a input and output : 5n from [0:inf)<br /> ttransit: transit time for changes at the output : 5n from [0:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4 |
---++ <a name="JKFF">JK-Flip Flop</a>
| *Module Name* | V_jk_ff |
| *Terminals* | q: logic output : output voltage<br /> qbar: inverse logic output : output voltage<br /> clk: clock terminal : input voltage<br /> j: data input : input voltage<br /> k: data input : input voltage |
| *Parameter* | tdelay: time between change on a input and output : 5n from [0:inf)<br /> ttransit: transit time for changes at the output : 5n from [0:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4 |
---++ <a name="RSFF">RS-Flip Flop</a>
| *Module Name* | V_rs_ff |
| *Terminals* | q: logic output : output voltage<br /> qbar: inverse logic output : output voltage<br /> set: data input : input voltage<br /> reset: data input : input voltage |
| *Parameter* | tdelay: time between change on a input and output : 5n from [0:inf)<br /> ttransit: transit time for changes at the output : 5n from [0:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4 |
---++ <a name="TFF">T-Flip Flop</a>
| *Module Name* | V_t_ff |
| *Terminals* | q: logic output : output voltage<br /> clk: clock terminal : input voltage |
| *Parameter* | tdelay: time between change on a input and output : 5n from [0:inf)<br /> ttransit: transit time for changes at the output : 5n from [0:inf)<br /> vout_high: high output voltage = 5.0<br /> vout_low: low output voltage = 0.0 from (-inf:vout_high)<br /> vth: input threshold voltage = 1.4<br /> q_init: integer initial value for q = 0 from [0:1] |
---++ <a name="ClkGen">Clock Generator</a>
| *Module Name* | clock_generator |
| *Terminals* | clk: terminal : output voltage |
| *Parameter* | clk_period: clock period = 10n from (0:inf)<br /> clk_ratio: ratio between low clock time and clock period = 0.5<br /> clk_high: high clock output = 5.0<br /> clk_low: low clock output = 0.0 from (-inf:clk_high)<br /> trise: rising time = 1n<br /> tfall: falling time = 1n |
---++ <a name="BER">Bit Error rate Calculator</a>
| *Module Name* | bit_error_rate |
| *Terminals* | in: input terminal : input voltage<br /> ref: reference terminal : input voltage |
| *Parameter* | period: clock period = 5n from (0:inf)<br /> vth: threshold for input bits = 2.5 |

-- Main.DavidMiller - 2011-03-01

Attachments

I	Attachment	Action	Size	Date	Who	Comment
va	and.va	manage	1.5 K	2012-09-14 - 15:48	DavidMiller	'and' module with variable number of input terminals
va	biterrorrate.va	manage	0.9 K	2012-09-14 - 15:48	DavidMiller	Bit error rate calculator model
va	clock_generator.va	manage	1.0 K	2012-09-14 - 15:48	DavidMiller	Clock generator for symmetric clock
va	d_ff.va	manage	0.9 K	2012-09-14 - 15:48	DavidMiller	D-Flip Flop
va	jk_ff.va	manage	1.1 K	2012-09-14 - 15:49	DavidMiller	JK-Flip Flop
va	nand.va	manage	1.5 K	2012-09-14 - 15:49	DavidMiller	'nand' module with variable number of input terminals
va	nor.va	manage	1.5 K	2012-09-14 - 15:49	DavidMiller	'nor' module with variable number of input terminals
va	not.va	manage	1.1 K	2012-09-14 - 15:50	DavidMiller	Inverter module with variable number of input and output terminals
va	or.va	manage	1.4 K	2012-09-14 - 15:50	DavidMiller	'or' module with variable number of input terminals
va	rs_ff.va	manage	1.8 K	2012-09-14 - 15:50	DavidMiller	RS-Flip Flop
va	t_ff.va	manage	0.9 K	2012-09-14 - 15:50	DavidMiller	T-Flip Flop
va	xnor.va	manage	1.5 K	2012-09-14 - 15:50	DavidMiller	'xnor' module with variable number of input terminals
va	xor.va	manage	1.5 K	2012-09-14 - 15:51	DavidMiller	'xor' module with variable number of input terminals

Topic revision: r3 - 2012-09-14 - 15:51:10 - DavidMiller

VerilogAMS