TWiki
>
P1800 Web
>
SystemVerilogAssertionCommittee
>
SVACMeetingMinutes
>
SV-AC_Minutes_2011_06_21
(2011-07-08,
ErikSeligman
)
(raw view)
E
dit
A
ttach
Minutes of SV-AC Meeting Date: 2011-06-21 Time: 16:00 UTC (9:00 PDT) Duration: 1.5 hours Dial-in information: -------------------- Meeting ID: 38198 Phone Number(s): 1-888-813-5316 Toll Free within North America Live Meeting: [[https://webjoin.intel.com/?passcode=4797656]] Agenda: ------- - Reminder of IEEE patent policy. See: http://standards.ieee.org/board/pat/pat-slideset.ppt - Minutes approval - Email ballot results Mantis 3069 Passed: 6y, 0n, 0a Mantis 3033 Failed: 0y, 5n, 1a - New issues - Issue resolution/discussion 3033: Allow procedural control statements is checkers 3552:Sequence methods // .triggered need further clarification - Enhancement progress update - Mantis status Attendance Record: ------------------ Legend: x = attended - = missed r = represented . = not yet a member v = valid voter (2 out of last 3 or 3/4 overall) n = not a valid voter t = chair eligible to vote only to make or break a tie Attendance re-initialized on 2010-07-06: v[xxx---xxxx-xxx-xxx...........................] Ashok Bhatt (Cadence) v[-xxxxxx-xxxxxxxxxx-xxx-xxxxxxxxx-x-xxxxx--xxx] Laurence Bisht (Intel) v[xxxxxxx-xxxxxxxxx-xxxxxxxxxxxx-xxxxxxxxxxxxx-] Eduard Cerny (Synopsys) v[xxxxx--------xx---xxx--x-xxxxxxx-xxxxx-xxxxxx] Ben Cohen (Accellera) n[--------------------------xx-x-xxx-x--xxxxxxx] Surrendra Dudani (Synopsys) v[xxxxx........................................] Shaun Feng (Freescale) n[-x--x-x-xxxx-x-x----x-x-x--xx---xxxx---x-xxxx] Dana Fisman (Synopsys) n[------------------------xxxxx-xxxx-x-xxxxxxxx] John Havlicek (Freescale) v[xxx-xx-xxxx-xxxxxxxxxxxxxxxx-xxx-xxxxxxxxxxxx] Tapan Kapoor (Cadence) v[-xxxxx-xxxx-x-x..............................] Jacob Katz (Intel) t[-xxx-xxxxxxxxxxxxxxxxxxxxxxx--xxxxxxxxxxxxxxx] Dmitry Korchemny (Intel ¿ Chair) v[x-xxxxx-xxxx-xxxxxxxxxxxxxxx--xxxxxx-xxxxxxxx] Scott Little (Freescale) v[xxxxxxxxx-xxxxxxxxxxxxxxxxx-xxxxxxxxx-xxxxxxx] Manisha Kulshrestha (Mentor Graphics) v[xxxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxx] Anupam Prabhakar (Mentor Graphics) n[x--xxx-xxxx-xxx-xxx--x-xx-xxx-xx--xxxxxxx-xxx] Erik Seligman (Intel) v[x-xxxxxxxxxx-x-xxx-xxxx-xxxx--xxxxxx-xxxxxxx.] Samik Sengupta (Synopsys) v[xxxxxxxxx-xxxxxxxxxxxxxxxxx-xxxxxxxxxxxxx-xxx] Tom Thatcher (Oracle ¿ Co-Chair) n[---------xx---xx-------x.....................] Srini Venkataramanan (CVC Pvt Ltd) |- attendance on 2011-06-21 |--- voting eligibility on 2011-06-21 Minutes: -------- - Reminder of IEEE patent policy. See: http://standards.ieee.org/board/pat/pat-slideset.ppt Participants were reminded of the IEEE patent policy. - Minutes approval Ben: Move to approve minutes Samik: Second Vote results: 9y, 0n, 1a 3033 Allow procedural control statements is checkers Ben: Proposal gave lots of rationale for why things are done a certain way. Rest of LRM doesn't do this. Erik: Yes, some of this should be moved to preamble of the proposal. Ben: Blocking assignments used as a variable. A good idea to allow blocking assignments. But only as a local variable. Tom: You can declare an automatic variable inside a for loop. Ben The idea would be to allow use as temporary variables. You can do this otherwise using a function call. Tom: My feedback comments regarding the always_latch were incorrect. No change to the proposal needed for the example with always_latch. Erik: Schedule discussion for when Dmitry comes back. - Issue resolution/discussion 3552 Was moved to SV-BC 3195 Local Variable flow out. Ben: Would like to revive this proposal. Erik: Will review this proposal Scott: Will review this proposal 3478 Make local values accessible. Ben: This seems to be a hole. Would like to fix it. Scott, Erik: This would be a new issue that we would need Sampled values in classes & constraints 2476: Generalized count-bits function Scott: Champions feedback was different this time. Neil only updated The Mantis items, He didn't send out e-mail Tom Will ask Neil about Champions feedback Erik: Dave rich opposed use of a bit vector argument (variable bit width) because vectors are usually extended when there is a mismatch. This function would be an exception: If the user specifies 2 bits, the value would not be extended to 4 bits, but used as is. He proposed a Logic queue. Or make it a constant 4-bit argument. Tom: If it is a constant 4-bit argument, then if a user specifed a 2-bit argument, it would be extended, and would likely contain a 0, which would give unexpected results. Scott: Of the given options, prefer the queue. Erik: Will update proposal with the queue idea. Probably will be ready by next meeting. 2412: Allow clock inference in sequences. Champions feedback: Anupam: Shalom's feedback: modules don't have arguments, they have ports. Anupam: Made an editorial change Manisha: What about checkers? Erik: BNF says that checkers have "ports" Scott: Is it proper to say "function instantiation?" Tom: Yes, because Verilog's original functions are static. Anupam: VPI section mentions function instnace Anupam: Maybe should change text to "function call". Manisha: Function call should be a more correct usage. 3552: Sequence methods .triggered() needs clarification Dave Rich posted a comment Manisha: One thing not clear Is Dave saying we should not define it? Or is he saying that this should be illegal? Ed: Right now, it's left open. Ed: Suggest in proposal that the "bad usage" comments be changed to "behavior not defined" Ed: Does example code occur in a module or an interface? What happens when this is an interface passed to a program? In a program, the "if" sthatement would be ok If in an interface passed to a module, then the "if" would probably not work. Ben: Could we test the code on a simulator? Ed: That's one approach. But we should study LRM to get an answer For this proposal, make the example into a module, then we don't have to worry about the Program case. 2412: Allow clock inference in sequences. Anupam: Has uploaded modified proposal. Ben: Prefer to e-mail vote it. Tom: Will call for an e-mail vote. Meeting adjouned.
E
dit
|
A
ttach
|
P
rint version
|
H
istory
: r2
<
r1
|
B
acklinks
|
V
iew topic
|
Ra
w
edit
|
M
ore topic actions
Topic revision: r2 - 2011-07-08 - 20:36:37 -
ErikSeligman
P1800
Log In
or
Register
P1800 Web
Create New Topic
Index
Search
Changes
Notifications
Statistics
Preferences
Webs
Main
P1076
Ballots
LCS2016_080
P10761
P1647
P16661
P1685
P1734
P1735
P1778
P1800
P1801
Sandbox
TWiki
VIP
VerilogAMS
Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki?
Send feedback