(r5) WaitLevel < P1076

P1076 Web>Vhdl2019CollectedRequirements>WaitLevel (revision 5) (raw view)~~EditAttach~~
---+ Level Sensitive Wait

%TOC%

---++ Proposal Information
   * Current Owner: Main.JimLewis, ...
   * Contributors: Main.JimLewis, ...
   * Date Proposed: 2014-June-22
   * Date Last Updated: 2020-October-30
   * Priority:
   * Complexity:
   * Focus: Testbench
   * Related Issues: loosely, but both are useful [[ExpressionsAndSignalParameters][Mapping Expressions to Signal Parameters]]
   * Competing Issues: None
---++ Requirement Summary

Level Sensitive Wait

See ISAC [[http://www.eda.org/isac/IRs-VHDL-2002/IR2108.txt][IR2108]]

The [[WaitRepeat]] proposes modifying the language syntax of the wait statement.

---++ A Code Solution

This can easily be accomplished with the code
<verbatim>
if A /= Level then
  wait until A = Level ;
end if; </verbatim>

However, what is being sought is a more concise solution.

---++ Encapsulation with a Procedure

If the following worked, it would be an acceptable solution. However while a signal input to an entity allows expressions with VHDL-2008, a signal input to a parameter of a subprogram does not.
<verbatim>procedure WaitLevel (
  signal condition : in boolean 
) is 
begin
  if not condition then
    wait until condition ;
  end if ; 
end procedure WaitLevel ; </verbatim>

General support issues: When an expression is passed as input signal parameter, it would have the default value of the type (here false) until a delta cycle passes. Here that works just fine.

---++ Language Based Solution

<verbatim>
wait when A /= '1' ; 
</verbatim>

Equivalent to and would be defined by the following transformation:
<verbatim>
if A /= '1' then
  wait until A = '1' ;
end if; </verbatim>

An explicit condition_clause (until) would replace the implicit condition clause and hence, 
<verbatim>
wait when A /= '1' until rising_edge(Clk) and C = '1' ; 
</verbatim>

Transforms to
<verbatim>
if A /= '1' then
  wait until rising_edge(Clk) and C = '1' ; 
end if; </verbatim>

It should be noted that the more likely form of the above is shown below.
"C" was used to demonstrate the full intent - there were historical misinterpretations
of "wait on A until B" as to whether "B" was in the sensitivity list or not (it is not).  

<verbatim>
wait when A /= '1' until rising_edge(Clk) and A = '1' ; 
</verbatim>


syntax:
<verbatim>
wait_statement ::=
    [ label : ] wait [ when_clause ] [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ;

when_clause ::= when condition

sensitivity_clause ::= on sensitivity_list

sensitivity_list ::= signal_name { , signal_name }

condition_clause ::= until condition

timeout_clause ::= for time_expression
</verbatim>

---++ Comments

-- Main.JimLewis - 2020-10-30  As I was coding, this popped into my thoughts, so I captured it.   Still forming thoughts about it.  

A process with a wait when may never wait, and hence, for simulators that report issues with a "possible infinite loop" will still report that if the only wait is a wait when.

-- Main.JimLewis - 2014-06-22 Personally I am not excited about a syntax based solution as it would potentially make the wait statement even more complex.  OTOH, allowing in parameter signals to have an expression and solving this using a procedure in a package would be a good solution.

---+++ Arguments Against

---++ Supporters
Topic revision: r1 - 2020-10-30 - 16:17:58 - TWikiGuest
P1076