Active IR List from VHDL-2008

Revised: -- JimLewis - 2014-06-22
Updated links: -- ErnstChristen - 2017-01-05

IRs accepted for consideration in VHDL-201X

These items have been forwarded from ISAC requests to be considered for the next language revision.

IR #	BugZ#	Link to Proposal	Problem to Solve	Description	Notes
2109	-	Enhance	Interface / Com	Semaphore with protected types
2033	-	Enhance		Incremental operator and auto subtype boundary wrap
2108	-	WaitLevel	Testbench Sync	Level sensitive check - A "wait" that checks condition before stopping	Referred to in: Wait with a repeat count
2003	-	MultiCyclePath		Specification of multi-cycle paths to synthesis tool w/o creating registers. Jim Lewis: During meeting how in general specify this and perhaps capture false paths as well and simulate them
2113	-	ReadRom	General	Init ROM / Array data structure with a file - syntax or library (types + std subprogs)
2119	-	DeferredSharedVariables	Interface / Com	Can't declare a protected type and object of that type in a single package
2121	275	Partially Connected Vectors in Port Map	General	Allow for vectors to have assigns and opens in the port map
2125	-	Std_ulogic, Resolved, and '-'	Interface / Com	Resolution of '-' and 'Z' is 'X", ok for RTL, but bad for testbenches?
2007	-	BidirectionalConnections		VHDL needs to be enhanced to allow the modeling of switches. (forward to VHDL-AMS?)
2009	-	ConditionalCompilation		New std package, containing tool and vendor identification information Needs to be considered in conjunction with conditional compilation. May need to be precompiler directives
2011	-	ComponentDerivedFromEntity		Syntax that creates a component declaration from an entity decalaration and puts it into a specified package
2012	-	UniqueCondition		Wants to remove the priority from if-elsif-elsif structures under some conditions. Proposes: "if elsor elsor".
2021	-	DynamicRewiring		Dynamic hardware construct
2025		ConditionalCompilation		"Generate" for sequential code (c.f. ConditionalCompilation)
2106		ConditionalCompilation		Desire preprocessor (macro/ifdef) support in VHDL
2034	-	ClockedShorthand		Introduce history attribute on signals to auto infer registers
2035	-	ClockedShorthand		new function "stages" automates pipelining
2041		Partiallyconnectedvectorsonportmap		Allow composite port subelements to be left open.
2060		Truth Tables		Include truth table for multi-input/multi-output logic.
2072		Operations on Ranges		Allow static operations on "ranges"
2089		Interfaces	Interfaces	Directional records
2100		Operators Overloading for Protected Types		Operator overloading for protected type methods
2076		Record Member Attribute		A member attribute for records.
2065		Relaxed Others Aggregate		OTHERS in aggregates too restrictive
2067		Interfaces		Enhancement: Logical link interface abstraction
2103		DynamicRewiring		Dynamic/run-time creation and destruction of components and connectivity
2130	239	Overload Assignment		Ability to overload the assignment operator := would be useful	Concerns
2132	240	FunctionKnowsVectorSize		Method to allow functions that return arrays to have knowledge of the target attributes
	295	RemoveConfigurationLibraryRequirement		Allow configurations for entities not in the same library
	294	Force and Out Ports		Force of an out port using mode is improperly defined
	293	Alternate Path Name		Issue with path_name and instance_name wrt VHDL-2008 generate labels
	292	ConfigureDirectInstantiation		Configure Architecture of Direct Entity Instantiation
	291	Composites of Protected Types		Allow composites to have elements that are protected types.
	290	Method Parameters that are Access Types		Allow method parameters to be of an access type.
	289	Fix2008ContextClause		Context declaration requirements are not uniform
	288	New Bit Literal Rules		Bit string literals not correctly defined
	287	Process all and global signals		process(all) non-parameter signal read error should be errorenous
	286	Fix2008LRM7321		incremental binding example is illegal
	285	Boolean TEXTIO Write		textio write[line,boolean...] is not backward compatible across language versions
	284	Fixed + Float Pkg updates		Sizing rules for fixed point reciprocal are wrong
	282	Package Name Capitalization		Give IEEE package names consistency capitalization
	281	Fixed + Float Pkg updates		Discrepancies between float_generic_pkg.vhdl and float_generic_pkg-body.vhdl (unresolved_unsigned vs unsigned)
	278 280	Precedence of Unary Logical Operations		Clarify precedence of logic reduction operators
	277	Read of bit_vector vs. std_ulogic_vector		Read of bit_vector and std_ulogic_vector differ slightly.
	276	StopReadOnTrailingUnderscore		'_' at the end of hex and octal reads
	259	User-Defined Attributes May Not Redefine Predefined Attributes		attribute declaration with same designator as a predefined attribute

IRs for 1076.6

IR #	BugZ#	Status	Responsible	Description	Notes
2114	-			1076.6-2004 section 8.6.5 Slice names is too restrictive.
2066				Support multidimensional arrays in IEEE Std 1076.6-2004

IRs Rejected

IR #	BugZ#	Status	Date	Description	Notes
2027	-	Reject	Aug 29, 2013	When loop index is static, drivers are created for each element of array
2131	233	Reject	Email	Vhpi_user.h requires enum types contents update/completion	Information available in parent.
2026	-	Reject	Aug 7, 2014	Upward propagating parameters	VHDL-2008 introduces external names to constants (including generics) that addresses this request. Hence, out generics would be a redundant feature
	283	Reject	May 1, 2014	?/= function in float_generic_pkg can give wrong answer	Resolved as Invalid

IRs Completed in VHDL-2008 by either Accellera VHDL WG or VASG

IR #	BugZ#	Status	Responsible	Description	Notes
2005	-	Done		sla operator behavior does not match typical hardware behavior Base language did not change. Instead it is fixed in packages. It is overloaded in numeric_bit_unsigned for bit vector. For std_logic_vector is not be defined unless numeric_std_unsigned is included.
2117	-	Done		Block comment is not there in vhdl
2118	-	Done, Duplicate		Typo in 9.2 Note 2
2006	-	Done		"else" in "if generate"?
2014	-	Done		Allowance of the keyword "all" in place of a sensitivity list is desirable
2015	-	Done		Generics should be able to incorporate other generics
2016	-	Done, Duplicate		Allowance of the keyword "all" in place of a sensitivity list is desirable
2017	-	Done, Duplicate		Generics should be able to incorporate other generics
2019	-	Done		Reading outputs from within architecture
2022	-	Done		Elements of constant composite to be locally static
2024	-	Done		VHDL needs encryption support
2046		Done		AKA Type Generics: Type independent ports and subprogram parameters
2088		Done		Formatted I/O
2054		Superceded		Individual assoc. rules for array formal are not valid
2063	? 42	Forwarded		Unconstrained array formals should not get subtype from actuals

IRs Completed in VHDL-2008 by ISAC

IR #	BugZ#	Description	Notes
1000		Accumulated typographical and terminology errors.
1044		Definition of 'HIGH and 'LOW in a null range
1070		VPI Issue 14 -- Prefixes in USE clauses
2000		Where may/must deferred constant declaration appear
2001		Resize not working in numeric_std.vhd (1076.3
2002		Resize(R.2) function in numeric_std.vhd does improper array length check
2004		Definition of SLA doesn't make sense
2008		Source value of undriven, non-sourced INOUT, OUT or BUFFER port
2010		The description of type/subtype relationship could be better
2013		Exact subtype "matching" for port associations
2018		Variable IN parameter should be no different than constant
2020		Keyword REPORT is over-used
2023		Add predefined array types for integer, boolean, real and time
2028		Clarify simulation cycle.
2029		Non-relevant words and paragraph.
2030		What signature does a method have
2031		"mod" function needed for TIME
2032 2032.1		Function "now" is not pure
2036		protected_type_declarative_item includes subprogram_specification
2037		Typo wrt now in the index
2038		Minor semantic errors
2039		Minor typos
2040		Problems with OTHERS in aggregates
2042		Architecture as a block causes problems
2043		Numeric VALUE attribute parameter can't have sign
2044		Deprecation of linkage ports affects boundary scan description language
2045		Add the ability to comment an entire block of code
2047		Backslash in extended identifiers
2048		Miscellaneous errors
2049		Circular definition of an event on a signal
2050		Definition of S'Last_Value was apparently broken in 1993
2051		Path_name and instance_name do not allow for protected types
2052		Path_name and instance_name don't deal with operator symbols
2053		Minor Typos in VHDL 2002 part 2
2055		Prohibition on assignment of protected types not normative
2056		Can an attribute name that denotes a function be used where a name is required?
2057		Access-typed parameters to predefined "=" and "/="
2058		Does USE of type name make operators and literals visible?
2059		Upper/lower case character mapping is not clear
2061		Default actions on severity flags is different between simulators
2062		Range staticness
2064		Type conversion of unconstrained output in a port map
2068		Entity instantiation with space before the entity name
2069		Visibility of generics in block configurations
2070		Support for floating point denormal numbers
2071		Indexed name in case expression
2073		Index constraints and discrete range conversions from universal_integer
2074		Problem with direct/select visibility in formal part
2075		Arrays with numeric and enumeration index types are not closely related
2077		Incorrect wording on some language constructs
2078		Allow attribute declaration/specification in package body
2079		Is TIME a locally static type?
2080		Case expression should include parenthesized expression
2081		The term ancestor is used where parent is meant
2082		Elaboration of unconstrained interface objects
2083		Generate index specification should be of same subtype as generate parameter
2084		A record "element" is not called a "field"
2085		What happens when a parameter of mode out is not assigned in a procedure?
2086		Incorrect description of type mark in disconnection specification
2087		Ambiguous rule for type of an alias declaration
2090		Signature in alias declaration for "not" wrong
2091		Translation between std_logic_vector based types and std_ulogic_vector
2092		Type conversions don't allow for null arrays
2093		Static type conversions and qualified expressions
2094		Attribute specifications of overloaded subprograms is limited
2095		What is the entity class of an enumeration literal?
2096		Error is ambiguous
2097		Operations with Array aggregates
2098		Ambiguity in definition of T'VAL for Physical types
2099		Alias declarations introduce homographs
2101		Type conversion - implicit refers to section 8.1.2 which doesn't exist
2104		Using a configuration to leave a design unbound
2105		Can't declare an alias of a character literal without using expanded name
2107		Editorial process dropped a \ from extended identifier example
2111		Unknown term used: selector
2115		Binding specification should be binding indication
2116		What is the direction of std_logic_vector & '0'
2120		How to access objects in higher level nested protected type
2122		Protected method has implied object parameter?
2123		Process resumption and callbacks
2124		Ordering of process execution and callbacks
2126		Concatenation ambiguity
2127		Possible LRM interpretation pitfall related to the predefined STANDARD package
2128		Shared Variable declarations in generate?
2129		Bad requirements to check exprs with access type sub exprs
2110		Implicit subtype conversions not defined
2112		Can attributes be applied to a signal on the entity within the architecture for that entity?
2102		Duplicate: Typo in Section 3.2.1. Example

Original Active IR list dated 18 June 2008