UCVHDL200xFT17CompositeInterfaceMode < P1076

P1076 Web>Vhdl2019CollectedRequirements>InterfaceAndBundleEnhancements>UCVHDL200xFT17CompositeInterfaceMode (2016-01-21, BrentHahoe) (raw view)EditAttach

---+ VHDL-200X  FT-17 Composite Interface Mode

---++ Enhancement Detail:

Give VHDL the ability to specify the IO mode 
of an element of a record.  Useful for testbenches
and system modeling.
<verbatim>
type IfRecType is record
  Sig1 : std_logic ;
  Sig2 : std_logic ;
  Sig3 : std_logic_vector(7 downto 0) ;
  Sig4 : std_logic_vector(7 downto 0) ;
end record ;

Mode IfRecType_Mode_Model1 : IfRecType := (
  Sig1 => in,
  Sig2 => out,
  Sig3 => inout, 
  Sig4 => in 
) ; 
Mode IfRecType_Mode_Model2 : IfRecType := (
  Sig1 => out,
  Sig2 => in,
  Sig3 => inout, 
  Sig4 => in 
) ; 

Entity Model1 is
port (
  IfRec1 : IfRecType_Model_Model1 : IfRecType ;
  . . .
</verbatim></sticky>

Topic revision: r2 - 2016-01-21 - 11:52:26 - BrentHahoe

P1076