(r55) UCComplexRTLSignalCPUInterface < P1076

P1076 Web>Vhdl2019CollectedRequirements>InterfaceAndBundleEnhancements>UCComplexRTLSignalCPUInterface (revision 55) (raw view)~~EditAttach~~
---+!! Complex RTL Record Based CPU Interface Use Case

%TOC%

---++ Introduction

The concept of this use case is to arbitrarily introduce a fairly complex block and interface structure in order to try and identify requirements that have hitherto been unforeseen.

---++ Assumptions

   * As per [[P1076.UCMinimalRTLSignalInterface#Assumptions][Minimal RTL Assumptions]].

---+++!! Additional

   * The composite mode *view* syntax has been expanded to specifically associate a *view* with its composite *type* or *subtype*.
      * *record view* _&lt;composite_view_identifier&gt;_ *of* _&lt;composite_subtype_name&gt;_ *is* %BR% ... %BR% *end* [ *record* ] *view* [ _&lt;composite_view_identifier&gt;_ ] ;
      * *array view* _&lt;composite_view_identifier&gt;_ *of* _&lt;composite_subtype_name&gt;_ *is* %BR% ... %BR% *end* [ *array* ] *view* [ _&lt;composite_view_identifier&gt;_ ] ;

   * Similar to the *entity(architecture)* syntax, the subtype name is linked to the view identifier with a bracketed syntax:
      * _&lt;composite_subtype_name&gt;_ ( _&lt;composite_mode_view_identifier&gt;_ )

   * The composite mode *view* syntax is required to support a *generic* functionality of the instantiated *entity* or *component* in order to provide instance identification.
   * To aid syntax parsing, a new keyword *element* has been added to differentiate the *element* *view* section from the *generic* section within a named mode *view* construct, e.g.:
<sticky><pre>
      <b>array view</b> <i>&lt;composite_view_identifier&gt;</i> <b>of</b> <i>&lt;composite_subtype_name&gt;</i> <b>is</b>
         <b>generic</b>(
            <i>&lt;generic_name&gt;</i> : <i>&lt;generic_subtype_name&gt;</i>
         );
         <b>element</b>(
            <i>&lt;element_name&gt;</i> <b>: view</b>   <i>&lt;composite_subtype_view_name&gt;</i>;
            <i>&lt;element_name&gt;</i> <b>: in</b>     <i>&lt;element_subtype_name&gt;</i>;
            <i>&lt;element_name&gt;</i> <b>: out</b>    <i>&lt;element_subtype_name&gt;</i>
         );
      <b>end array view</b> <i>&lt;composite_view_identifier&gt;</i>;
</pre></sticky>
   * In order to be able to link a composite mode *view* within a *view* declaration, the passing of a *generic* value through to the sub-view is done as an instantiation using a *generic map* syntax.

   * A new mode *null* is proposed to allow elements of a composite to be disconnected from a given instantiation. A *null* *port* may be driven or read from either side, but no information passes through a *null* *port*.

---++ Use Case Example

A complex CPU bus interface with multiple slave entities, multiple master entities and an arbiter entity. The design is also split into hierarchical sublevel entities in order to try and identify extra support requirements for *record* and *array* based *view* modes. A compressed tarball with the VHDL files (both 2008 version and according to the proposal) can be found [[%ATTACHURL%/../InterfaceAndBundleEnhancements/ComplexRTL.tar.gz][here]].

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUInterfaceTop.png" height="522" />

---+++ CPU Bus Package

   * In order to make declarations visible across hierarchies, they are defined within a *package*:

<sticky><pre>
   <b>package</b> cpu_bus_pkg
      <b>generic</b>(
         masters_max_jg : <b>positive</b>;
         slaves_max_jg  : <b>positive</b>;
         awidth_jg      : <b>positive</b>;
         dwidth_jg      : <b>positive</b>
      );
      <b>is</b>
      <b>subtype</b>  masters_total_jrt <b>is natural range</b> masters_max_jg - 1 <b>downto</b> 0;

      <b>constant</b> slaves_total_jc   <b> : positive</b> := slaves_max_jg     -- individual slaves
                                              + masters_max_jg    -- master's slave return
                                              + 1;                -- arbiter's slave return
      <b>subtype</b>  slaves_total_jrt  <b>is natural range</b> slaves_total_jc - 1 <b>downto</b> 0;

      <b>subtype</b>  addr_jrt          <b>is natural range</b> awidth_jg - 1 <b>downto</b> 0;
      <b>subtype</b>  data_jrt          <b>is natural range</b> dwidth_jg - 1 <b>downto</b> 0;

      <b>subtype</b>  master_ctrl_vst   <b>is std_logic_vector</b>(masters_total_jrt);
      <b>subtype</b>  slave_ctrl_vst    <b>is std_logic_vector</b>(slaves_total_jrt);

      <b>subtype</b>  addr_vst          <b>is std_logic_vector</b>(addr_jrt);
      <b>subtype</b>  data_vst          <b>is std_logic_vector</b>(data_jrt);
</pre></sticky>

   * Having defined the subtypes relating to the *package* *generic* data, now define the various *record* types to be used.
   * The concept is to have a *record* data structure for each of the master, slave and arbiter interfaces and then incorporate these records hierarchically into a higher level CPU bus *record* structure.

---++++ Array and Record Structures

   * The master record defines all signals driven from the current master.
   * There is an array (vector) of slave enables :

<sticky><pre>
      <b>type</b> master_r <b>is</b>                      -- Master record
         <b>record</b>
            addr_vl <b>:</b> addr_vst;             -- Address bus to slave devices
            data_vl <b>:</b> data_vst;             -- Data bus from master to slave
            we_l    <b>: std_logic</b>;            -- Write enable from master to slave
            en_vl   <b>:</b> slave_ctrl_vst;       -- Slave enables from master to slave
         <b>end record</b> master_r;
</pre></sticky>

<img width="865" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUMasterRecord.png" height="300" />

   * The slave composite is an array of slave records. Each slave drives back its own set of signals to the current master.

<sticky><pre>
      <b>type</b> slave_r <b>is</b>                        -- Slave record
         <b>record</b>
            data_vl <b>:</b> data_vst;              -- Data bus from slave to master
            ack_l   <b>: std_logic</b>;             -- Acknowledge to master from slave
            err_l   <b>: std_logic</b>;             -- Error report to master from slave
         <b>end record</b> slave_r;

      <b>type</b> slave_a <b>is</b>
         <b>array</b>(slaves_total_jrt) <b>of</b> slave_r; -- Array of slave return records
</pre></sticky>

<img width="860" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUSlaveArrayAndRecord.png" height="337" />

   * The arbiter takes inputs from each master and allocates the bus to one master.
   * It then multiplexes this master record onto the main master record.
   * The arbiter composite is an array of records containing each master's record along with its bus grant/request signals.

<sticky><pre>
      <b>type</b> arbiter_r <b>is</b>                      -- Arbiter record and array
         <b>record</b>
            master_rl   <b>:</b> master_r;          -- Master record to the arbiter
            bus_req_l   <b>: std_logic</b>;         -- Bus request from master
            bus_grnt_l  <b>: std_logic</b>;         -- Bus grants to master
         <b>end record</b> arbiter_r;

      <b>type</b> arbiter_a <b>is</b>
         <b>array</b>masters_total_jrt) <b>of</b> arbiter_r; -- Array of arbiter records
</pre></sticky>

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUArbiterArrayAndRecord.png" height="320" />

   * The main CPU bus record incorporates the arbiter array element, the master record element and the slave array element composites.

   * The arbiter array routes the various masters' outputs to the arbiter instance.
   * The arbiter grants the bus to the selected master and drives its outputs onto the CPU bus record's master record element.

   * The master record drives the control elements to each slave instance - address & data, write enable and an array of slave enables.

   * The slave array routes slave instance return elements to the selected master - return data, acknowledge and error controls

<sticky><pre>
      <b>type</b> cpu_bus_r <b>is</b>                     -- Bus interface record
         <b>record</b>
            arbiter_al : arbiter_a;           -- Arbiter array of arbiter master control records
            master_rl  : master_r;            -- Master record to slaves
            slave_al   : slave_a;             -- Array of slave records to master
         <b>end record</b> cpu_bus_r;
</pre></sticky>

<img width="888" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUBusRecord.png" height="538" />

---++++ Array and Record Mode Views

   * Define the mode views on the CPU Bus for each slave, master and the arbiter.

---+++++!! CPU Bus - Slave Mode View

   * Define an *array* and a *record* mode view for slave instances.

   * The *array* view needs a generic aspect that will be selected via a generic on the instantiation of the slave entity.
   * This generic controls which slave *record* element of the *array* is driven back to the master.
   * All other *array* elements instead of being left dangling/unconnected, are terminated using the new *null* mode.
   * The integer *generic* is instance related.

   * In order to achieve the propagation of generics through the mode *view* hierarchy, we need to be able to map the generic from the CPU bus *record* *view* declaration down to the slave *array* *view* declaration.
   * The hierarchical views can be seen as an instantiation of a declaration within another declaration and therefore use a *generic map* syntax to pass through *generic* values???

   * The *null* mode can be thought of using the analogy of an instance & component compared to a socket & chip on a PCB. %BR% A *null* port mode is equivalent to cutting the pin from the chip. %BR% Once inserted in the socket, the PCB still sees the node but it is not driven, allowing another instance to drive this element of the interface. %BR% Internally, the chip may drive the pin, but it is not passed through to the socket. %BR% Reading the port results in a default element type ('U' in Std_logic) as nothing can pass in either direction across a *null* mode *port*.

<sticky><pre>
      <b>array view</b> s_slave_avw <b>of</b> slave_a <b>is</b>
         <b>generic</b>(
            slave_id_jg : slaves_total_jrt
         );
         <b>element</b>(
            slave_id_jg <b>: buffer</b> slave_r;
            <b>others      : null</b>   slave_r
         );
      <b>end array view</b> s_slave_avw;
</pre></sticky>

   * Define top level slave *record* mode *view* for the CPU bus *record*.

<sticky><pre>
      <b>record view</b> slave_rvw <b>of</b> cpu_bus_r <b>is</b>
         <b>generic</b>(
            slave_id_jg : slaves_total_jrt
         );
         <b>element</b>(
            arbiter_al <b>: null</b>   arbiter_a;
            master_rl  <b>: in</b>     master_r;
            slave_al   <b>: view</b>   slave_a(
                                   s_slave_avw(
                                      <b>generic map</b>(
                                         slave_id_jg => slave_id_jg
         )                      )  )  );
      <b>end record view</b> slave_rvw;
</pre></sticky>

   * To be able to distinquish the *generic* section of the *record* *view* from the element mode views, add a new *element* keyword to encapsulate these as a new syntactical section.
   * The 'slave_avw' *array* *view* then has a *generic* *map* section to pass the 'slave_id_jg' *integer* *generic* through to this level.

<img width="857" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUBusSlaveModeView.png" height="526" />

---+++++!! CPU Bus - Master Mode View

   * Declare all mode views to define an interface for master instances.

   * Define master *record* mode *view* for the arbiter *record*.
   * The master *record* and bus request control are driven out to the arbiter.
   * The bus grant control is received back from the arbiter.

<sticky><pre>
      <b>record view</b> m_arbiter_rvw <b>of</b> arbiter_r <b>is</b>
         <b>element</b>(
            master_rl  <b>: buffer</b> master_r;
            bus_req_l  <b>: buffer std_logic</b>;
            bus_grnt_l <b>: in     std_logic</b>
         );
      <b>end record view</b> m_arbiter_rvw;
</pre></sticky>

   * Define master *array* mode *view* for the arbiter *array*.
   * The *array* element is selected by the intsance's master *generic* integer value.
   * All other *array* elements are connect as *null* modes.

<sticky><pre>
      <b>array view</b> m_arbiter_avw <b>of</b> arbiter_a <b>is</b>
         <b>generic</b>(
            master_id_jg : <b>positive</b>
         );
         <b>element</b>(
            master_id_jg <b>: view</b>   arbiter_r(m_arbiter_rvw) ;
            <b>others       : null</b>   arbiter_r
         );
      <b>end array view</b> m_arbiter_rvw;
</pre></sticky>

   * Define master *array* mode *view* for the slave *array*.
   * The *array* element is selected by the intsance's slave *generic* integer value and is driven out to the slected master (i.e. when this instance is not selected as master and is therefore acting as a slave instance).
   * All other *array* elements are connect as *in* modes (i.e. slave inputs when this instance is granted access as a master).

<sticky><pre>
      <b>array view</b> m_slave_avw <b>of</b> slave_a <b>is</b>
         <b>generic</b>(
            slave_id_jg : slaves_total_jrt
         );
         <b>element</b>(
            slave_id_jg <b>: buffer</b> slave_r;
            <b>others      : in</b>     slave_r
         );
      <b>end array view</b> m_slave_rvw;
</pre></sticky>

   * Define top level master *record* mode *view* for the CPU bus *record*.

<sticky><pre>
      <b>record view</b> master_rvw <b>of</b> cpu_bus_r <b>is</b>
         <b>generic</b>(
            slave_id_jg  : slaves_total_jrt;
            master_id_jg : masters_total_jrt
         );
         <b>element</b>(
            arbiter_al <b>: view</b>   arbiter_r(
                                   m_arbiter_avw(
                                      <b>generic map</b>(
                                         master_id_jg => master_id_jg
                                )  )  );
            master_rl  <b>: in</b>     master_r;
            slave_al   <b>: view</b>   slave_a(
                                   m_slave_avw(
                                      <b>generic map</b>(
                                         slave_id_jg => slave_id_jg
         )                      )  )  );
      <b>end record view</b> master_rvw;
</pre></sticky>

<img width="857" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUBusMasterModeView.png" height="526" />

---+++++!! CPU Bus - Arbiter Mode View

   * Declare all mode views to define an interface for the arbiter instance.

   * Declare the individual *record* *view* from each master to the arbiter.
   * This arbiter *record* *view* includes a master *record* input element, a bus request input element and a return bus grant output element.

<sticky><pre>
      <b>record view</b> a_arbiter_rvw <b>of</b> arbiter_r <b>is</b>
         <b>element</b>(
            master_rl  <b>: in</b>     master_r;
            bus_req_l  <b>: in     std_logic</b>;
            bus_grnt_l <b>: buffer std_logic</b>
         );
      <b>end record view</b> a_arbiter_rvw;
</pre></sticky>

   * Define the *array* *view* of these arbiter records from each master.

<sticky><pre>
      <b>array view</b> a_arbiter_avw <b>of</b> arbiter_a <b>is</b>
         <b>element</b>(
            <b>others    : view</b>    arbiter_r(a_arbiter_rvw)
         );
      <b>end array view</b> a_arbiter_rvw;
</pre></sticky>

   * Define top level arbiter *record* mode *view* for the CPU bus *record*.

   * The arbiter *array* *view* interfaces to each master instance.
   * The master *record* element drives the master *record* out to all slave interfaces.
   * The slave *array* *view* acts identically to any other slave interface (in this case providing access to the arbiter instance).

<sticky><pre>
      <b>record view</b> arbiter_rvw <b>of</b> cpu_bus_r <b>is</b>
         <b>generic</b>(
            slave_id_jg  : slaves_total_jrt
         );
         <b>element</b>(
            arbiter_al  <b>: view</b>   arbiter_r(a_arbiter_rvw);
            master_rl   <b>: buffer</b> master_r;
            slave_al    <b>: view</b>   slave_a(
                                    s_slave_avw(
                                       <b>generic map</b>(
                                          slave_id_jg => slave_id_jg
         )                       )  )  );
      <b>end record view</b> arbiter_grnt_rvw;
</pre></sticky>

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUBusArbiterModeView.png" height="546" />

---+++ Master, slave and arbiter entities

   * Instantiate the interface *package* based on the top level hierarchy as detailed at the beginning of this document - 2 masters, 8 slaves and a single arbiter.

<sticky><pre>
   <b>package</b> cpu_bus_2m8s_pkg <b>is new</b> cpu_bus_pkg
      <b>generic map</b>(
         masters_max_jg => 2,
         slaves_max_jg  => 8,
         awidth_jg      => 12,
         dwidth_jg      => 16
      );
</pre></sticky>

---++++!! Generic slave entity

   * Use the new instantiated *package* and declare a *generic* slave *entity*.

<sticky><pre>
     <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
     <b>entity</b> slave_ent <b>is</b>
       <b>generic</b> (
         slave_id_jg : slaves_total_jrt
       );
       <b>port</b>(
         rst_i       <b>: in     std_logic</b>
         clk_i       <b>: in     std_logic</b>;
         cpu_bus_rif <b>: view</b>   slave_r(
                                 slave_rvw(
                                    <b>generic map</b>(
                                       slave_id_jg => slave_id_jg
         )                       )  )  );
     <b>end entity</b> slave_ent;

     <b>architecture</b> rtl_arch <b>of</b> slave_ent <b>is</b>
         <b>signal</b> addr_vs     <b>:</b> cpu_bus_2m8s_pkg.addr_vst;
         <b>signal</b> data_in_vs  <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> we_s        <b>: std_logic</b>;
         <b>signal</b> en_s        <b>: std_logic</b>;

         <b>signal</b> data_out_vs <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> ack_s       <b>: std_logic</b>;
         <b>signal</b> err_s       <b>: std_logic</b>;
   <b>begin</b>
</pre></sticky>

   * Compose/decompose the interface record: 
      * Receive the master data with write enable and slave enable signals from the arbiter.
      * Return the acknowledge and error status signals with the slave return data to the selected master.

<sticky><pre>
      addr_vs    <= cpu_bus_rif.master_rl.addr_vl;
      data_in_vs <= cpu_bus_rif.master_rl.data_vl;
      we_s       <= cpu_bus_rif.master_rl.we_l;
      en_s       <= cpu_bus_rif.master_rl.en_vl(slave_id_jg);

      cpu_bus_rif.slave_al(slave_id_jg).data_vl <= data_out_vs;
      cpu_bus_rif.slave_al(slave_id_jg).ack_l   <= ack_s;
      cpu_bus_rif.slave_al(slave_id_jg).err_l   <= err_s;

      ...

     <b>end architecture</b> rtl_arch;
</pre></sticky>

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUSlaveEntity.png" height="546" />

---++++!! Generic master entity

   * Use the new instantiated *package* and declare a *generic* master *entity*.

<sticky><pre>
     <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
     <b>entity</b> master_ent <b>is</b>
       <b>generic</b> (
         slave_id_jg  : slaves_total_jrt;
         master_id_jg : masters_total_jrt
       );
       <b>port</b> (
         rst_i       <b>: in     std_logic</b>
         clk_i       <b>: in     std_logic</b>;
         cpu_bus_rif <b>: view</b>   master_r(
                                 master_rvw(
                                    <b>generic map</b>(
                                       slave_id_jg  => slave_id_jg,
                                       master_id_jg => master_id_jg
         )                       )  )  );
     <b>end entity</b> master_ent;

     <b>architecture</b> rtl_arch  <b>of</b> master_ent <b>is</b>
         -- Master bus and controls to/from arbiter instance
         <b>signal</b> addr_vs     <b>:</b> cpu_bus_2m8s_pkg.addr_vst;
         <b>signal</b> data_vs     <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> we_s        <b>: std_logic</b>;
         <b>signal</b> en_vs       <b>:</b> cpu_bus_2m8s_pkg.slave_ctrl_vst;

         <b>signal</b> bus_req_s   <b>: std_logic</b>;
         <b>signal</b> bus_grnt_s  <b>: std_logic</b>;

         -- Selected master bus input from arbiter instance
         <b>signal</b> addr_in_vs  <b>:</b> cpu_bus_2m8s_pkg.addr_vst;
         <b>signal</b> data_in_vs  <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> we_in_s     <b>: std_logic</b>;
         <b>signal</b> en_in_vs    <b>:</b> cpu_bus_2m8s_pkg.slave_ctrl_vst;

         -- Return slave bus output when not selected as master
         <b>signal</b> data_out_vs <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> ack_s       <b>: std_logic</b>;
         <b>signal</b> err_s       <b>: std_logic</b>;

         -- Input slave array when selected as master
         <b>signal</b> s_slave_as <b>:</b> cpu_bus_2m8s_pkg.slave_a;
   <b>begin</b>
</pre></sticky>

   * Compose/decompose the interface record: 
      * Transmit the master data with write enable and slave enable controls out to the arbiter, alongside a bus request control also to the arbiter instance. Receive the bus grant control back from the arbiter instance.
      * Receive the master data with write enable and slave enable signals from the arbiter.
      * Return the acknowledge and error status signals with the slave return data when not the selected master.

<sticky><pre>
      -- Arbiter interface
      cpu_bus_rif.arbiter_al(master_id_jg).master_rl.addr_vl <= addr_vs;
      cpu_bus_rif.arbiter_al(master_id_jg).master_rl.data_vl <= data_vs;
      cpu_bus_rif.arbiter_al(master_id_jg).master_rl.we_l    <= we_s;
      cpu_bus_rif.arbiter_al(master_id_jg).master_rl.en_vl   <= en_vs;

      cpu_bus_rif.arbiter_al(master_id_jg).bus_req_l         <= bus_req_s;

      bus_grnt_s <= cpu_bus_rif.arbiter_al(master_id_jg).bus_grnt_l;


      -- Master interface from arbiter
      addr_in_vs <= cpu_bus_rif.master_rl.addr_in_vl;
      data_in_vs <= cpu_bus_rif.master_rl.data_in_vl;
      we_in_s    <= cpu_bus_rif.master_rl.we_in_l;
      en_in_s    <= cpu_bus_rif.master_rl.en_in_vl(slave_id_jg);


      -- Slave interface to other selected master 
      cpu_bus_rif.slave_al(slave_id_jg).data_vl <= data_out_vs;
      cpu_bus_rif.slave_al(slave_id_jg).ack_l   <= ack_out_s;
      cpu_bus_rif.slave_al(slave_id_jg).err_l   <= err_out_s;

      -- Slave interface from all slaves when selected as master
      s_slave_as <= cpu_bus_rif.slave_al;

      ...

     <b>end architecture</b> rtl_arch;
</pre></sticky>

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUMasterEntity.png" height="546" />

---++++!! Arbiter entity

   * Use the new instantiated *package* and declare the arbiter *entity*.

<sticky><pre>
     <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
     <b>entity</b> arbiter_ent <b>is</b>
       <b>generic</b> (
         slave_id_jg  : slaves_total_jrt
       );
       <b>port</b> (
         rst_i       <b>: in     std_logic</b>
         clk_i       <b>: in     std_logic</b>;
         cpu_bus_rif <b>: view</b>   arbiter_r(
                                 arbiter_rvw(
                                    <b>generic map</b>(
                                       slave_id_jg => slave_id_jg
         )                       )  )  );
     <b>end entity</b> arbiter_ent;

     <b>architecture</b> rtl_arch  <b>of</b> arbiter_ent <b>is</b>
         -- Master bus and controls to/from arbiter instance
         <b>signal</b> arbiter_as  <b>:</b> cpu_bus_2m8s_pkg.arbiter_a;
         <b>signal</b> bus_req_vs  <b>: std_logic_vector</b>(masters_total_jrt);
         <b>signal</b> bus_grnt_vs <b>: std_logic_vector</b>(masters_total_jrt);

         -- Selected master bus input from arbiter array
         <b>signal</b> addr_in_vs  <b>:</b> cpu_bus_2m8s_pkg.addr_vst;
         <b>signal</b> data_in_vs  <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> we_in_s     <b>: std_logic</b>;
         <b>signal</b> en_in_vs    <b>:</b> cpu_bus_2m8s_pkg.slave_ctrl_vst;

         -- Return slave bus output when not selected as master
         <b>signal</b> data_out_vs <b>:</b> cpu_bus_2m8s_pkg.data_vst;
         <b>signal</b> ack_s       <b>: std_logic</b>;
         <b>signal</b> err_s       <b>: std_logic</b>;
   <b>begin</b>
</pre></sticky>

   * Compose/decompose the interface record: 
      * Receive each master's data, write enable and slave enable signals with its bus request signal.
      * Send the bus grant back to the selected master instance.
      * Transmit the master data with write enable and slave enable signals from the arbiter via the CPU Bus master *record* element.
      * Return slave data along with acknowledge and error status signals when accessed by the selected master.

<sticky><pre>
      -- Arbiter interface
      arbiter_as <= cpu_bus_rif.arbiter_al

      -- Generate bus request vector and return bus grant vector
      for i_jv in masters_total_jrt loop
         bus_req_vs(i_jv - 1) <= cpu_bus_rif.arbiter_al(i_jv - 1).bus_grnt_l;

         if (i_jv - 1 = m_select_jg - 1) then
            cpu_bus_rif.arbiter_al(i_jv - 1).bus_grnt_l <= '1';
         else
            cpu_bus_rif.arbiter_al(i_jv - 1).bus_grnt_l <= '0';
         end if;
      end loop;

      -- Selected master bus for arbiter slave accesses
      addr_in_vs <= arbiter_as(m_select_jg - 1).master_rl.addr_vl;
      data_in_vs <= arbiter_as(m_select_jg - 1).master_rl.data_vl;
      we_in_s    <= arbiter_as(m_select_jg - 1).master_rl.we_l;
      en_in_vs   <= arbiter_as(m_select_jg - 1).master_rl.en_vl;


      -- Selected master interface from arbiter to slaves on CPU bus interface
      cpu_bus_rif.master_rl <= arbiter_as(m_select_jg - 1).master_rl;


      -- Arbiter slave access to selected master 
      cpu_bus_rif.slave_al(slave_id_jg).data_vl <= data_out_vs;
      cpu_bus_rif.slave_al(slave_id_jg).ack_l   <= ack_out_s;
      cpu_bus_rif.slave_al(slave_id_jg).err_l   <= err_out_s;

      ...

     <b>end architecture</b> rtl_arch;
</pre></sticky>

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUArbiterEntity.png" height="546" />

---+++ Alternative mode view declared within an entity declaration

The bracketed syntax:
   * _&lt;composite_subtype_name&gt;_ ( _&lt;composite_mode_view_identifier&gt;_ )

is still maintained but without a composite mode *view* identifier. Instead the syntax starts with the new *element* keyword.

The *generic* section is not required here (should it be allowed/disallowed?) because of the scope of the instantiation *generic* making it visible throughout the whole of the *entity* declaration section.

---++++!! Alternative slave entity declaration

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> slave_ent <b>is</b>
      <b>generic(</b>
         slave_id_jg : slaves_total_jrt
      );
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: null</b> arbiter_a;
                                    master_rl  <b>: in</b>   master_r;
                                    slave_al   <b>: view</b> slave_a(
                                                         <b>element</b>(
                                                            slave_id_jg  <b>: buffer</b> slave_r;
                                                            others    <b>: null</b>   slave_r
      )                       )  )                    )  );
   <b>end entity</b> slave_ent;
</pre></sticky>

---++++!! Alternative master entity declaration

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> master_ent <b>is</b>
      <b>generic(</b>
         slave_id_jg  : slaves_total_jrt;
         master_id_jg : masters_total_jrt
      );
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: view</b> arbiter_a(
                                                         <b>element</b>(
                                                            master_id_jg <b>: view</b>   arbiter_r;
                                                               <b>element</b>(
                                                                  master_rl   <b>: buffer</b> master_r;
                                                                  bus_req_l   <b>: buffer std_logic</b>;
                                                                  bus_grnt_l  <b>: in     std_logic</b>
                                                               );
                                                            others    <b>: null</b>   arbiter_r
                                                         );
                                    master_rl  <b>: in</b>   master_r;
                                    slave_al   <b>: view</b> slave_a(
                                                         <b>element</b>(
                                                            slave_id_jg  <b>: buffer</b> slave_r;
                                                            others    <b>: in</b>     slave_r
      )                       )  )                    )  );
   <b>end entity</b> master_ent;
</pre></sticky>

---++++!! Alternative arbiter entity declaration

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> arbiter_ent <b>is</b>
      <b>generic(</b>
         slave_id_jg : slaves_total_jrt
      );
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: view</b> arbiter_a(
                                                         <b>element</b>(
                                                            others <b>: view</b>   arbiter_r;
                                                               <b>element</b>(
                                                                  master_rl   <b>: in</b>     master_r;
                                                                  bus_req_l   <b>: in     std_logic</b>;
                                                                  bus_grnt_l  <b>: buffer std_logic</b>
                                                         )     );
                                    master_rl  <b>: buffer</b> master_r;
                                    slave_al   <b>: view</b>   slave_a(
                                                           <b>element</b>(
                                                              slave_id_jg  <b>: buffer</b> slave_r;
                                                              others       <b>: null</b>   slave_r
      )                       )  )                      )  );
   <b>end entity</b> arbiter_ent;
</pre></sticky>

---++ Top Level Hierarchy Instantiations

   * Instantiate the three second level hierarchies:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUInterfaceTop.png" height="522" />

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> CPU_Bus_top_ent
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic</b>
      );
   <b>end entity</b> CPU_Bus_top_ent;
</pre></sticky>

   * Define the test bench *architecture* and declare the necessary signals:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> CPU_Bus_top_ent <b>is</b>
      <b>signal</b> rst_s      <b>: std_logic</b>;
      <b>signal</b> clk_s      <b>: std_logic</b>;
      <b>signal</b> cpu_bus_rs <b>:</b> cpu_bus_2m8s_pkg.cpu_bus_r;
</pre></sticky>

   * Instantiate the top level instances

<sticky><pre>
   begin
      Sonly_inst <b>: entity</b> Sonly_ent
         <b>port map</b>(
            rst_i       => rst_s,
            clk_i       => clk_s,
            cpu_bus_rif => cpu_bus_rs
         );

      MplusS_inst <b>: entity</b> MplusS_ent
         <b>port map</b>(
            rst_i       => rst_s,
            clk_i       => clk_s,
            cpu_bus_rif => cpu_bus_rs
         );

      AMandS_inst <b>: entity</b> AMandS_ent
         <b>port map</b>(
            rst_i       => rst_s,
            clk_i       => clk_s,
            cpu_bus_rif => cpu_bus_rs
         );

      slave_inst2 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 1
         )
         <b>port map</b>(
            rst_i       => rst_s,
            clk_i       => clk_s,
            cpu_bus_rif => cpu_bus_rs
         );

      slave_inst7 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 6
         )
         <b>port map</b>(
            rst_i       => rst_s,
            clk_i       => clk_s,
            cpu_bus_rif => cpu_bus_rs
         );

      ...

     <b>end architecture</b> rtl_arch;
</pre></sticky>

   * The second hierarchy level entities are better handled in terms of mode views within the *entity* declaration. Unlike the multiple master, and slave generic instances, there is only a single instance of each of these.

---+++ Slave only Hierarchy Level Entity

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUSonlyEntity.png" height="522" />

   * Declare the mode *view* within the *entity*:

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> Sonly_ent <b>is</b>
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: null</b> arbiter_a;
                                    master_rl  <b>: in</b>   master_r;
                                    slave_al   <b>: view</b> slave_a(
                                                         <b>element</b>(
                                                            0      <b>: buffer</b> slave_r;
                                                            5      <b>: buffer</b> slave_r;
                                                            others <b>: null</b>   slave_r
      )                       )  )                    )  );
   <b>end entity</b> Sonly_ent;
</pre></sticky>

   * And instantiate the slave instances:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> Sonly_ent <b>is</b>

   begin
      slave_inst1 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 0
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );

      slave_inst6 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 5
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );
     <b>end architecture</b> rtl_arch;
</pre></sticky>

---+++ Master plus Slave Hierarchy Level Entity

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUMplusSEntity.png" height="522" />

   * Declare the mode *view* within the *entity*:

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> MplusS_ent <b>is</b>
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: view</b> arbiter_a(
                                                         <b>element</b>(
                                                            0      <b>: view</b>   arbiter_r;
                                                               <b>element</b>(
                                                                  master_rl   <b>: buffer</b> master_r;
                                                                  bus_req_l   <b>: buffer std_logic</b>;
                                                                  bus_grnt_l  <b>: in     std_logic</b>
                                                               );
                                                            others <b>: null</b>   arbiter_r
                                                         );
                                    master_rl  <b>: in</b>   master_r;
                                    slave_al   <b>: view</b> slave_a(
                                                         <b>element</b>(
                                                            2      <b>: buffer</b> slave_r;
                                                            4      <b>: buffer</b> slave_r;
                                                            8      <b>: buffer</b> slave_r;
                                                            others <b>: in</b>     slave_r
      )                       )  )                    )  );
   <b>end entity</b> MplusS_ent;
</pre></sticky>

   * And instantiate the slave instances:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> MplusS_ent <b>is</b>

   begin
      master_inst1 <b>: entity</b> master_ent
         <b>generic map</b>(
            slave_id_jg  => 8,
            master_id_jg => 0
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );

      slave_inst3 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 2
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );

      slave_inst5 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 4
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );
     <b>end architecture</b> rtl_arch;
</pre></sticky>

---+++ Arbiter, Master and Slave Hierarchy Level Entity

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_CPUAMandSEntity.png" height="522" />

   * Declare the mode *view* within the *entity*:

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> AMandS_ent <b>is</b>
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: view</b> arbiter_a(
                                                         <b>element</b>(
                                                            0 <b>: view</b>   arbiter_r;
                                                               <b>element</b>(
                                                                  master_rl   <b>: in</b>     master_r;
                                                                  bus_req_l   <b>: in     std_logic</b>;
                                                                  bus_grnt_l  <b>: buffer std_logic</b>
                                                            1 <b>: null</b>   arbiter_r
                                                         )     );
                                    master_rl  <b>: buffer</b> master_r;
                                    slave_al   <b>: view</b>   slave_a(
                                                           <b>element</b>(
                                                              10     <b>: buffer</b> slave_r;
                                                              9      <b>: buffer</b> slave_r;
                                                              3      <b>: buffer</b> slave_r;
                                                              7      <b>: buffer</b> slave_r;
                                                              others <b>: in</b>     slave_r
      )                       )  )                      )  );
   <b>end entity</b> AMandS_ent;
</pre></sticky>

   * And instantiate the slave instances:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> AMandS_ent <b>is</b>

   begin
      arbiter_inst <b>: entity</b> arbiter_ent
         <b>generic map</b>(
            slave_id_jg  => 10
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );

      master_inst2 <b>: entity</b> master_ent
         <b>generic map</b>(
            slave_id_jg  => 9,
            master_id_jg => 1
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );

      slave_inst4 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 3
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );

      slave_inst8 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 7
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            cpu_bus_rif => cpu_bus_rif
         );
     <b>end architecture</b> rtl_arch;
</pre></sticky>

---++ Conclusions

   * For simple RTL use, a new interface construct is not required. %BR% New interface named view constructs, along with their interface composite type declarations, can be grouped together using an existing *package* construct.

   * The *generic* functionality associated with the instantiation identification of an *entity*, requires the new composite *type* named mode *view* to be capable of supporting this at the instantiation construct level (as opposed to being handled within a *generic package* instantiation).

   * There might be some usefulness to be gained in providing an *attribute* to return a mode *view* for an hierarchical entity, based on the usage of the mode views within its instantiated structure (e.g. whether a driver is present on an interface *type element*).

   * The use of a non-named mode *view* (i.e. in situ declaration within the *entity*) provides visibility of the I/O structure at the *entity/architecture* source level and might be preferred by some. %BR% It can also provide a shorter form of mode *view* declaration for hierarchical level feed-through *port* declarations.

---+ Appendices

---++ Current VHDL-2008 Capability and Implementation

   * The current implementation of the VHDL language limits this design because of the lack of mode directionality within composite type elements when traversing *port/parameter* interface boundaries of an *entity* or subprogram respectively.

---+++!! VHDL-2008 Slave Entity

   * The slave *entity* requires a master *record* as an input in order to drive an access and replies back with its own slave *record* as an output.

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUSlaveEntity.png" height="546" />

   * Use a VHDL-2008 version of the generic *package* and declare a *generic* slave *entity*.

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> slave_ent <b>is</b>
      <b>generic</b> (
         slave_id_jg : vhdl2008_cpu_bus_2m8s_pkg.slaves_total_jrt
      );
      <b>port</b> (
         rst_i     <b>: in     std_logic</b>
         clk_i     <b>: in     std_logic</b>;
         master_ri <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.master_r;
         slave_rb  <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r
      );
      <b>alias</b> addr_vs     <b>is</b> master_ri.addr_vl;
      <b>alias</b> data_in_vs  <b>is</b> master_ri.data_vl;
      <b>alias</b> we_s        <b>is</b> master_ri.we_l;
      <b>alias</b> en_s        <b>is</b> en_vl(slave_id_jg);

      <b>alias</b> data_out_vs <b>is</b> slave_rb.data_vl;
      <b>alias</b> ack_s       <b>is</b> slave_rb.ack_l;
      <b>alias</b> err_s       <b>is</b> slave_rb.err_l;

   <b>end entity</b> slave_ent;
</pre></sticky>

---+++!! VHDL-2008 Master Entity

   * The master *entity* requires a master *record* as an input in order to respond to an access (when not selected as the current master) and replies back with its own slave *record* output.

   * When selected as the current master, it requires the *array* of all slave *record* replies as an input in order to process all slave accesses.

   * In order to gain control as master, the master *record* is grouped with the bus request control in an *arbiter* record output which is then routed to the arbiter instantiation.

   * The arbiter replies via the bus grant vector (*array*) input. The master's own bus grant is selected using the master_id_jg *generic*.

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUMasterEntity.png" height="546" />

   * Use a VHDL-2008 version of the generic *package* and declare a *generic* slave *entity*.

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> master_ent <b>is</b>
      <b>generic</b> (
         slave_id_jg  : vhdl2008_cpu_bus_2m8s_pkg.slaves_total_jrt
         master_id_jg : vhdl2008_cpu_bus_2m8s_pkg.masters_total_jrt
      );
      <b>port</b> (
         rst_i       <b>: in     std_logic</b>
         clk_i       <b>: in     std_logic</b>;
         bus_grnt_vi <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.master_ctrl_vst;
         arbiter_rb  <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.arbiter_r
         master_ri   <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.master_r;
         slave_ai    <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.slave_a;
         slave_rb    <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r
      );
      <b>alias</b> master_op_rs <b>is</b> arbiter_rb.master_rl;
      <b>alias</b> bus_req_s    <b>is</b> arbiter_rb.bus_req_l;

      <b>alias</b> bus_req_s    <b>is</b> bus_grnt_vi(master_id_jg);

      <b>alias</b> addr_vs      <b>is</b> master_ri.addr_vl;
      <b>alias</b> data_in_vs   <b>is</b> master_ri.data_vl;
      <b>alias</b> we_s         <b>is</b> master_ri.we_l;
      <b>alias</b> en_s         <b>is</b> master_ri.en_vl(slave_id_jg);

      <b>alias</b> data_out_vs  <b>is</b> slave_rb.data_vl;
      <b>alias</b> ack_s        <b>is</b> slave_rb.ack_l;
      <b>alias</b> err_s        <b>is</b> slave_rb.err_l;

   <b>end entity</b> master_ent;
</pre></sticky>

---+++!! VHDL-2008 Arbiter Entity

   * The arbiter *entity* responds to an access from its internally selected master *record* and replies back with its own slave *record* output.

   * The arbiter receives the *array* of all arbiter *record* elements (containing a master *record* and bus request element) as an input. These are used to process access requests and grant control to a single master.

   * The bus grant vector is output to all master instances.

   * The select master's master *record* is driven out to all slave instances.

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUArbiterEntity.png" height="546" />

   * Use a VHDL-2008 version of the generic *package* and declare a *generic* slave *entity*.

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> arbiter_ent <b>is</b>
      <b>generic</b> (
         slave_id_jg  : vhdl2008_cpu_bus_2m8s_pkg.slaves_total_jrt
         master_id_jg : vhdl2008_cpu_bus_2m8s_pkg.masters_total_jrt
      );
      <b>port</b> (
         rst_i       <b>: in     std_logic</b>
         clk_i       <b>: in     std_logic</b>;
         bus_grnt_vb <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.master_ctrl_vst;
         arbiter_ai  <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.arbiter_a
         master_rb   <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.master_r;
         slave_rb    <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r
      );
      <b>alias</b> addr_vs      <b>is</b> master_rb.addr_vl;
      <b>alias</b> data_in_vs   <b>is</b> master_rb.data_vl;
      <b>alias</b> we_s         <b>is</b> master_rb.we_l;
      <b>alias</b> en_s         <b>is</b> master_rb.en_vl(slave_id_jg);

      <b>alias</b> data_out_vs  <b>is</b> slave_rb.data_vl;
      <b>alias</b> ack_s        <b>is</b> slave_rb.ack_l;
      <b>alias</b> err_s        <b>is</b> slave_rb.err_l;

   <b>end entity</b> arbiter_ent;
</pre></sticky>

---+++!! VHDL-2008 Slave-only Entity

   * The slave only *entity* is required to drive the two slave *record* outputs. They are composed into the slave *array* bus at the parent level and then routed to the currently selected master.

   * The master *record* is an input which drives accesses to the two slave instantiations.

<img width="856" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUSonlyEntity.png" height="546" />

   * Use a VHDL-2008 version of the generic *package* and declare a *generic* slave *entity*.

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> Sonly_ent <b>is</b>
      <b>port(</b>
         rst_i      <b>: in     std_logic</b>
         clk_i      <b>: in     std_logic</b>;
         master_ri  <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.master_r;
         slave_1_rb <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r;
         slave_6_rb <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r
      );
   <b>end entity</b> Sonly_ent;
</pre></sticky>

   * And instantiate the slave instances:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> Sonly_ent <b>is</b>

   begin
      slave_inst1 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 0
         )
         <b>port map</b>(
            rst_i     => rst_i,
            clk_i     => clk_i,
            master_ri => master_ri,
            slave_rb  => slave_1_rb
         );

      slave_inst6 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 5
         )
         <b>port map</b>(
            rst_i     => rst_i,
            clk_i     => clk_i,
            master_ri => master_ri,
            slave_rb  => slave_6_rb
         );
     <b>end architecture</b> rtl_arch;
</pre></sticky>

---+++!! VHDL-2008 Master plus Slave Hierarchy Level Entity

   * The master plus slave *entity* is required to drive the three slave *record* outputs (two from its slaves and one from its master). %BR% They are composed into the slave *array* bus at the parent level and then routed to the currently selected master.

   * The slave *array* is an input to the internal master instantiation and provides access replies from all slave instantiations.

   * The arbiter *record* output bundles the internal master instantiation's master *record* and bus request control which is routed to the arbiter instance externally.

   * The returned bus grant vector input is routed internally to the master instance.

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUMplusSEntity.png" height="522" />

   * Declare the mode *view* within the *entity*:

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> MplusS_ent <b>is</b>
      <b>port(</b>
         rst_i        <b>: in     std_logic</b>
         clk_i        <b>: in     std_logic</b>;
         bus_grnt_vi  <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.master_ctrl_vst;
         arbiter_1_rb <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.arbiter_r;
         master_ri    <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.master_r;
         slave_ai     <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.slave_a;
         slave_3_rb   <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r;
         slave_5_rb   <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r;
         slave_9_rb   <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r
   <b>end entity</b> MplusS_ent;
</pre></sticky>

   * And instantiate the slave instances:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> MplusS_ent <b>is</b>

   begin
      master_inst1 <b>: entity</b> master_ent
         <b>generic map</b>(
            slave_id_jg  => 8,
            master_id_jg => 0
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            bus_grnt_vi => bus_grnt_vi,
            arbiter_rb  => arbiter_1_rb,
            master_ri   => master_ri,
            slave_ai    => slave_ai,
            slave_rb    => slave_9_rb
         );

      slave_inst3 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 2
         )
         <b>port map</b>(
            rst_i     => rst_i,
            master_ri => master_ri,
            slave_rb  => slave_3_rb
         );

      slave_inst5 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 4
         )
         <b>port map</b>(
            rst_i     => rst_i,
            master_ri => master_ri,
            slave_rb  => slave_5_rb
         );
     <b>end architecture</b> rtl_arch;
</pre></sticky>

---+++!! VHDL-2008 Arbiter, Master and Slave Hierarchy Level Entity

   * The arbiter, master and slave *entity* is required to drive the four slave *record* outputs (two from its slaves, one from its master and one from the arbiter). %BR% They are composed into the slave *array* bus at the parent level and then routed to the currently selected master.

   * The slave *array* is an input to the internal master instantiation and provides access replies from all slave instantiations.

   * The master *record* is an output (from the internal arbiter instance) which drives accesses to the external (as well as internal) slave instantiations.

   * The arbiter *record* input bundles the external master instantiation's master *record* and bus request control which is routed to the arbiter instance internally.

   * The bus grant vector output is routed to the external master instance.

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUAMandSEntity.png" height="522" />

   * Declare the mode *view* within the *entity*:

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> AMandS_ent <b>is</b>
      <b>port(</b>
         rst_i        <b>: in     std_logic;</b>
         clk_i        <b>: in     std_logic;</b>
         bus_grnt_vb  <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.master_ctrl_vst;
         arbiter_1_ri <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.arbiter_r;
         master_rb    <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.master_r;
         slave_ai     <b>: in</b>     vhdl2008_cpu_bus_2m8s_pkg.slave_a;
         slave_4_rb   <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r;
         slave_8_rb   <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r;
         slave_10_rb  <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r;
         slave_11_rb  <b>: buffer</b> vhdl2008_cpu_bus_2m8s_pkg.slave_r
   <b>end entity</b> AMandS_ent;
</pre></sticky>

   * And instantiate the slave instances:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> AMandS_ent <b>is</b>

      <b>signal</b> arbiter_as <b>:</b> vhdl2008_cpu_bus_2m8s_pkg.arbiter_a;

   begin

      arbiter_as(0) <= arbiter_1_ri;

      arbiter_inst <b>: entity</b> arbiter_ent
         <b>generic map</b>(
            slave_id_jg  => 10
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            bus_grnt_vb => bus_grnt_vb,
            arbiter_ai  => arbiter_as,
            master_rb   => master_rb,
            slave_rb    => slave_11_rb
         );

      master_inst2 <b>: entity</b> master_ent
         <b>generic map</b>(
            slave_id_jg  => 9,
            master_id_jg => 1
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            bus_grnt_vi => bus_grnt_vb,
            arbiter_rb  => arbiter_as(1),
            master_ri   => master_rb,
            slave_ai    => slave_ai,
            slave_rb    => slave_10_rb
         );

      slave_inst4 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 3
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            master_ri => master_rb,
            slave_rb  => slave_4_rb
         );

      slave_inst8 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 7
         )
         <b>port map</b>(
            rst_i       => rst_i,
            clk_i       => clk_i,
            master_ri => master_rb,
            slave_rb  => slave_8_rb
         );
     <b>end architecture</b> rtl_arch;
</pre></sticky>

---+++!! VHDL-2008 Top Level Hierarchy Instantiations

   * Instantiate the three second level hierarchies and two slaves at the top level.

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_VHDL2008CPUInterfaceTop.png" height="522" />

<sticky><pre>
   <b>use</b> work.vhdl2008_cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> CPU_Bus_top_ent
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic</b>
      );
   <b>end entity</b> CPU_Bus_top_ent;
</pre></sticky>

   * Define the test bench *architecture* and declare the necessary signals:

<sticky><pre>
   <b>architecture</b> rtl_arch <b>of</b> CPU_Bus_top_ent <b>is</b>
      <b>signal</b> rst_s        <b>: std_logic</b>;
      <b>signal</b> clk_s        <b>: std_logic</b>;
      <b>signal</b> bus_grnt_vs  <b>:</b> vhdl2008_cpu_bus_2m8s_pkg.master_ctrl_vst;
      <b>signal</b> arbiter_1_rs <b>:</b> vhdl2008_cpu_bus_2m8s_pkg.cpu_bus_r;
      <b>signal</b> master_rs    <b>:</b> vhdl2008_cpu_bus_2m8s_pkg.master_r;
      <b>signal</b> slave_as     <b>:</b> vhdl2008_cpu_bus_2m8s_pkg.slave_a;

   begin
      Sonly_inst <b>: entity</b> Sonly_ent
         <b>port map</b>(
            rst_i        => rst_s,
            clk_i        => clk_s,
            master_ri    => master_rs,
            slave_1_rb   => slave_as(0),
            slave_6_rb   => slave_as(5)
         );

      MplusS_inst <b>: entity</b> MplusS_ent
         <b>port map</b>(
            rst_i        => rst_s,
            clk_i        => clk_s,
            bus_grnt_vi  => bus_grnt_vs,
            arbiter_1_rb => arbiter_1_rs,
            master_ri    => master_rs,
            slave_ai     => slave_as,
            slave_3_rb   => slave_as(2),
            slave_5_rb   => slave_as(4),
            slave_9_rb   => slave_as(8)
         );

      AMandS_inst <b>: entity</b> AMandS_ent
         <b>port map</b>(
            rst_i        => rst_s,
            clk_i        => clk_s,
            bus_grnt_vb  => bus_grnt_vs,
            arbiter_1_r1 => arbiter_1_rs,
            master_rb    => master_rs,
            slave_ai     => slave_as,
            slave_4_rb   => slave_as(3),
            slave_8_rb   => slave_as(8),
            slave_10_rb  => slave_as(9),
            slave_11_rb  => slave_as(10)
         );

      slave_inst2 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 1
         )
         <b>port map</b>(
            rst_i     => rst_s,
            clk_i     => clk_s,
            master_ri => master_rs,
            slave_rb  => slave_as(1)
         );

      slave_inst7 <b>: entity</b> slave_ent
         <b>generic map</b>(
            slave_id_jg => 6
         )
         <b>port map</b>(
            rst_i     => rst_s,
            clk_i     => clk_s,
            master_ri => master_rs,
            slave_rb  => slave_as(6)
         );

      ...

     <b>end architecture</b> rtl_arch;
</pre></sticky>

---++ Proposed Additional Syntax

   * This is an attempt to define the proposed syntax in BNF productions.

   * The BNF productions are for an RTL solution and define the syntax of directional mode control for elements of composite types based (initially) on an *entity* *signal* *port* interface.

   * This is a simplex format in that it does not include all the modifications to existing productions defining where these new productions may syntactically be used.

---

   * *interface_signal_declaration:* This is the start of the syntax changes and adds the additional *signal* *view* syntax as an option to that of the *signal* mode used in the definition of an interface *port*.

<sticky><pre>
   <a name="interface_signal_declaration"></a>interface_signal_declaration ::=
         [ <font color="LightSalmon"><b>signal</b></font> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>:</b></font> [ <a href="#mode">mode</a> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> [ <font color="LightSalmon"><b>bus</b></font> ] [ <font color="LightSalmon"><b>:=</b></font> <font color="LimeGreen"><i>static_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#expression">expression</a> ]
         | [ <font color="LightSalmon"><b>signal</b></font> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>: view</b></font> <font color="LimeGreen"><i> composite_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> <font color="LightSalmon"><b>(</b></font> <a href="#mode_view_clause">mode_view_clause</a> <font color="LightSalmon"><b>)</b></font>
</pre></sticky>

   * The mode *view* is defined using the composite *type* identifier to reference a *view* associated with that *type*. The *view* is referenced as a mode *view* clause.

---

   * *mode_view_clause:* The mode *view* clause defines two options.

<sticky><pre>
   <a name="mode_view_clause"></a>mode_view_clause ::=
         <font color="LimeGreen"><i>mode_view_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#indentifier">indentifier</a> [<font color="LightSalmon"><b> ( </b></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#generic_map_aspect">generic_map_aspect</a><font color="LightSalmon"><b> )</b></font> ]
         | <font color="LimeGreen"><i>formal_</i></font><a href="#composite_element_clause">composite_element_clause</a>
</pre></sticky>

   * The first references a named mode *view* declaration with an option to include a *generic* *map*. This is to enable the passing of an *entity* based *generic* through to the named mode *view*.

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> master_ent <b>is</b>
      <b>generic</b> (
         slave_id_jg  : slaves_total_jrt;
         master_id_jg : masters_total_jrt
      );
      <b>port</b> (
         rst_i       <b>: in     std_logic</b>
         clk_i       <b>: in     std_logic</b>;
         cpu_bus_rif <b>: view</b>   master_r(
                                 master_rvw(
                                    <b>generic map</b>(
                                       slave_id_jg  => slave_id_jg,
                                       master_id_jg => master_id_jg
         )                       )  )  );
     <b>end entity</b> master_ent;
</pre></sticky>

   * The second object allows for an unnamed mode *view* to be declared in place within the *entity* declaration and is defined as a composite *element* clause.

<sticky><pre>
   <b>use</b> work.cpu_bus_2m8s_pkg.<b>all</b>
   <b>entity</b> arbiter_ent <b>is</b>
      <b>generic(</b>
         slave_id_jg : slaves_total_jrt
      );
      <b>port(</b>
         rst_i       <b>: in     std_logic;</b>
         clk_i       <b>: in     std_logic;</b>
         cpu_bus_rif <b>: view</b>   cpu_bus_r(
                                 <b>element(</b>
                                    arbiter_al <b>: view</b> arbiter_a(
                                                         <b>element</b>(
                                                            others <b>: view</b>   arbiter_r;
                                                               <b>element</b>(
                                                                  master_rl   <b>: in</b>     master_r;
                                                                  bus_req_l   <b>: in     std_logic</b>;
                                                                  bus_grnt_l  <b>: buffer std_logic</b>
                                                         )     );
                                    master_rl  <b>: buffer</b> master_r;
                                    slave_al   <b>: view</b>   slave_a(
                                                           <b>element</b>(
                                                              slave_id_jg  <b>: buffer</b> slave_r;
                                                              others       <b>: null</b>   slave_r
      )                       )  )                      )  );
   <b>end entity</b> arbiter_ent;
</pre></sticky>

---

   * *mode_view_declaration:* The mode *view* declaration defines a named mode view, usually within a *package/package body* structure. This enables it to be referenced within scope at differing hierarchical levels of a design. %BR% The mode *view* is defined as a named *view* of a composite *type*. %BR% It encapsulates the ability to include an optional *generic* clause section along with the composite *element* clause.

<sticky><pre>
   <a name="mode_view_declaration"></a>mode_view_declaration ::=
         [ <font color="LightSalmon"><b>record</b></font> | <font color="LightSalmon"><b>array</b></font> ]<font color="LightSalmon"><b> view </b></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier">identifier</a><font color="LightSalmon"><b> of </b></font><font color="LimeGreen"><i>composite_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a><font color="LightSalmon"><b> is</b></font>
                  [ <font color="LimeGreen"><i>formal_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#generic_clause">generic_clause</a> ]
                  <font color="LimeGreen"><i>formal_</i></font><a href="#composite_element_clause">composite_element_clause</a>
         <font color="LightSalmon"><b>end</b></font> [ <font color="LightSalmon"><b>record</b></font> | <font color="LightSalmon"><b>array</b></font> ] <font color="LightSalmon"><b>view</b></font> [ <font color="LimeGreen"><i>mode_view_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#simple_name">simple_name</a> ] <font color="LightSalmon"><b>;</b></font>
</pre></sticky>

   * These declarations can be recursive:

<sticky><pre>
      <b>record view</b> slave_rvw <b>of</b> cpu_bus_r <b>is</b>
         <b>generic</b>(
            slave_id_jg : slaves_total_jrt
         );
         <b>element</b>(
            arbiter_al <b>: null</b>   arbiter_a;
            master_rl  <b>: in</b>     master_r;
            slave_al   <b>: view</b>   slave_a(
                                   s_slave_avw(
                                      <b>generic map</b>(
                                         slave_id_jg => slave_id_jg
         )                      )  )  );
      <b>end record view</b> slave_rvw;
</pre></sticky>

---

   * *composite_element_clause:* %BR% *composite_element_list:* %BR% *composite_element_declaration:*

<sticky><pre>
   <a name="composite_element_clause"></a>composite_element_clause ::=
         <font color="LightSalmon"><b>element ( </b></font><a href="#composite_element_list">composite_element_list</a><font color="LightSalmon"><b> ) ;</b></font>
</pre></sticky>

<sticky><pre>
   <a name="composite_element_declaration"></a>composite_element_declaration ::=
         <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>:</b></font> [ <a href="#mode">mode</a> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> [ <font color="LightSalmon"><b>bus</b></font> ] [ <font color="LightSalmon"><b>:=</b></font> <font color="LimeGreen"><i>static_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#expression">expression</a> ]
         | <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>: view</b></font> <font color="LimeGreen"><i> composite_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> <font color="LightSalmon"><b>(</b></font> <a href="#mode_view_clause">mode_view_clause</a> <font color="LightSalmon"><b>)</b></font>
</pre></sticky>

<sticky><pre>
   <a name="composite_element_list"></a>composite_element_list ::=
         <a href="#composite_element_declaration">composite_element_declaration</a> { <font color="LightSalmon"><b>; </b></font><a href="#composite_element_declaration">composite_element_declaration</a> }
</pre></sticky>

   * These productions define the mode of each *element* of the referenced composite *type*.

---

   * *mode:* The final production expands the mode kinds with the addition of the *null* mode. %BR% This provides the disconnection of the *port* within the *entity* from the parent hierarchy in which it is instantiated. %BR% The *port* appears to be connected but no information can be passed (in either direction) through it.

<sticky><pre>
   <a name="mode"></a>mode ::= <font color="LightSalmon"><b>in</b></font> | <font color="LightSalmon"><b>out</b></font> | <font color="LightSalmon"><b>inout</b></font> | <font color="LightSalmon"><b>buffer</b></font> | <font color="LightSalmon"><b>linkage</b></font> | <font color="LightSalmon"><b>null</b></font>
</pre></sticky>

   * Its use is intended to accommodate the termination of any unused 'dangling' elements of a complete composite *type* connection on a *port* mode *view*.

---+++!! Additional and Modified BNF Productions

   * This is an alphabetical list of the additional and modified BNF productions.

   * The productions are hyperlinked and will link through to the [[P1076.BNFVHDL2008][VHDL 2008 BNF productions here.]]

<sticky><pre>
   <a name="composite_element_clause"></a>composite_element_clause ::=
         <font color="LightSalmon"><b>element ( </b></font><a href="#composite_element_list">composite_element_list</a><font color="LightSalmon"><b> ) ;</b></font>
</pre></sticky>

<sticky><pre>
   <a name="composite_element_declaration"></a>composite_element_declaration ::=
         <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>:</b></font> [ <a href="#mode">mode</a> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> [ <font color="LightSalmon"><b>bus</b></font> ] [ <font color="LightSalmon"><b>:=</b></font> <font color="LimeGreen"><i>static_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#expression">expression</a> ]
         | <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>: view</b></font> <font color="LimeGreen"><i> composite_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> <font color="LightSalmon"><b>(</b></font> <a href="#mode_view_clause">mode_view_clause</a> <font color="LightSalmon"><b>)</b></font>
</pre></sticky>

<sticky><pre>
   <a name="composite_element_list"></a>composite_element_list ::=
         <a href="#composite_element_declaration">composite_element_declaration</a> { <font color="LightSalmon"><b>; </b></font><a href="#composite_element_declaration">composite_element_declaration</a> }
</pre></sticky>

<sticky><pre>
   <a name="interface_signal_declaration"></a>interface_signal_declaration ::=
         [ <font color="LightSalmon"><b>signal</b></font> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>:</b></font> [ <a href="#mode">mode</a> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> [ <font color="LightSalmon"><b>bus</b></font> ] [ <font color="LightSalmon"><b>:=</b></font> <font color="LimeGreen"><i>static_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#expression">expression</a> ]
         | [ <font color="LightSalmon"><b>signal</b></font> ] <a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier_list">identifier_list</a> <font color="LightSalmon"><b>: view</b></font> <font color="LimeGreen"><i> composite_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a> <font color="LightSalmon"><b>(</b></font> <a href="#mode_view_clause">mode_view_clause</a> <font color="LightSalmon"><b>)</b></font>
</pre></sticky>

<sticky><pre>
   <a name="mode"></a>mode ::= <font color="LightSalmon"><b>in</b></font> | <font color="LightSalmon"><b>out</b></font> | <font color="LightSalmon"><b>inout</b></font> | <font color="LightSalmon"><b>buffer</b></font> | <font color="LightSalmon"><b>linkage</b></font> | <font color="LightSalmon"><b>null</b></font>
</pre></sticky>

<sticky><pre>
   <a name="mode_view_clause"></a>mode_view_clause ::=
         <font color="LimeGreen"><i>mode_view_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#indentifier">indentifier</a> [<font color="LightSalmon"><b> ( </b></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#generic_map_aspect">generic_map_aspect</a><font color="LightSalmon"><b> )</b></font> ]
         | <font color="LimeGreen"><i>formal_</i></font><a href="#composite_element_clause">composite_element_clause</a>
</pre></sticky>

<sticky><pre>
   <a name="mode_view_declaration"></a>mode_view_declaration ::=
         [ <font color="LightSalmon"><b>record</b></font> | <font color="LightSalmon"><b>array</b></font> ]<font color="LightSalmon"><b> view </b></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#identifier">identifier</a><font color="LightSalmon"><b> of </b></font><font color="LimeGreen"><i>composite_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#subtype_indication">subtype_indication</a><font color="LightSalmon"><b> is</b></font>
                  [ <font color="LimeGreen"><i>formal_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#generic_clause">generic_clause</a> ]
                  <font color="LimeGreen"><i>formal_</i></font><a href="#composite_element_clause">composite_element_clause</a>
         <font color="LightSalmon"><b>end</b></font> [ <font color="LightSalmon"><b>record</b></font> | <font color="LightSalmon"><b>array</b></font> ] <font color="LightSalmon"><b>view</b></font> [ <font color="LimeGreen"><i>mode_view_</i></font><a href="http://www.eda.org/twiki/bin/view.cgi/Sandbox/BNFVHDL2008#simple_name">simple_name</a> ] <font color="LightSalmon"><b>;</b></font>
</pre></sticky>

---++ Real World Examples

In a recent WG meeting, an interest was expressed as to seeing how new
directional composite objects could be used.

---+++ AMBA AHB-Lite Interface

Shown below is the standard block diagram as shown in the AMBA AHB-Lite
Protocol Specification.

Example code for this block structure is %M%[[UCComplexRTLSignalCPUInterfaceAHBLcode][here]].

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite.png" height="522" />

The following diagram details the slave multiplexor function in more detail:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_Multiplexor.png" height="522" />

---++++ AHB-Lite Master Interface

The I/O structure of a master block is shown below:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_Master.png" height="522" />

---++++ AHB-Lite Slave Interface

The I/O structure of a slave block is shown below:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_Slave.png" height="522" />

---++++ AHB-Lite Signal Descriptions

| *Global signals:* | | |
| *Name*              | *Source*         | *Description* |
| <b>HCLK</b>         | Clock source     | The bus clock times all bus transfers. All signal timings are related to the rising edge of <b>HCLK</b>. |
| <b>HRESETn</b>      | Reset controller | The bus reset signal is active LOW and resets the system and the bus. This is the only active LOW AHB-Lite signal. |
| | | |
| *Master signals:* | | |
| *Name*              | *Destination*    | *Description* |
| <b>HADDR[31:0]</b>  | Slave and %BR% \
                            decoder      | The 32-bit system address bus. |
| <b>HBURST[2:0]</b>  | Slave            | The burst type indicates if the transfer is a single transfer or forms part of a burst. %BR% \
                                           Fixed length bursts of 4, 8, and 16 beats are supported. The burst can be incrementing or wrapping. Incrementing bursts of undefined length are also supported. |
| <b>HMASTLOCK</b>    | Slave            | When HIGH, this signal indicates that the current transfer is part of a locked sequence. It has the same timing as the address and control signals. |
| <b>HPROT[3:0]</b>   | Slave            | The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wants to implement some level of protection. %BR% \
                                           The signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a privileged mode access or user mode access. For masters with a memory management unit these signals also indicate whether the current access is cacheable or bufferable. |
| <b>HSIZE[2:0]</b>   | Slave            | Indicates the size of the transfer, that is typically byte, halfword, or word. The protocol allows for larger transfer sizes up to a maximum of 1024 bits. |
| <b>HTRANS[1:0]</b>  | Slave            |>> Indicates the transfer type of the current transfer. This can be:
   * IDLE
   * BUSY
   * NONSEQUENTIAL
   * SEQUENTIAL <<|
| <b>HWDATA[31:0]</b> | Slave            | The write data bus transfers data from the master to the slaves during write operations. A minimum data bus width of 32 bits is recommended. However, this can be extended to enable higher bandwidth operation. |
| <b>HWRITE</b>       | Slave            | Indicates the transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer. It has the same timing as the address signals, however, it must remain constant throughout a burst transfer. |
| | | |
| *Slave signals:* | | |
| *Name*              | *Destination*    | *Description* |
| <b>HRDATA[31:0]</b> | Multiplexor      | During read operations, the read data bus transfers data from the selected slave to the multiplexor. The multiplexor then transfers the data to the master. %BR% \
                                           A minimum data bus width of 32 bits is recommended. However, this can be extended to enable higher bandwidth operation. |
| <b>HREADYOUT</b>    | Multiplexor      | When HIGH, the <b>HREADYOUT</b> signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. |
| <b>HRESP</b>        | Multiplexor      | The transfer response, after passing through the multiplexor, provides the master with additional information on the status of a transfer. %BR% \
                                           When LOW, the <b>HRESP</b> signal indicates that the transfer status is OKAY. %BR% \
                                           When HIGH, the <b>HRESP</b> signal indicates that the transfer status is ERROR. |
| | | |
| *Decoder signals:* | | |
| *Name*              | *Destination*    | *Description* |
| <b>HSELx</b>        | Slave            | Each AHB-Lite slave has its own slave select signal <b>HSELx</b> and this signal indicates that the current transfer is intended for the selected slave. When the slave is initially selected, it must also monitor the status of <b>HREADY</b> to ensure that the previous bus transfer has completed, before it responds to the current transfer. %BR% \
                                           The <b>HSELx</b> signal is a combinatorial decode of the address bus. |
| | | |
| *Multiplexor signals:* | | |
| *Name*              | *Destination*    | *Description* |
| <b>HRDATA[31:0]</b> | Master           | Read data bus, selected by the decoder. |
| <b>HREADY</b>       | Master and slave | When HIGH, the <b>HREADY</b> signal indicates to the master and all slaves, that the previous transfer is complete. |
| <b>HRESP</b>        | Master           | Transfer response, selected by the decoder. |

---+++ Modified AHB-Lite Interface Structure

---++++ Single Master Interface Structure

Below is this standard block diagram modified to provide a simpler structure at
the top level by pushing the decoder and multiplexor down into the Master block.
This adaption does require Slave blocks to have generic identifiers in order
to be able to select their own elements within the interface composite structures.

Example code for this modified block structure is %M%[[UCComplexRTLSignalCPUInterfaceAHBLcodeMod][here]].

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_Modified.png" height="522" />

Advantages:
   * This gives a much cleaner and simpler interconnect code at the top \
     structural level. (There may be many interfaces at the top level.)
   * Interfacing of the slaves to the bus is handled by each instance's \
     generic ID.
   * Functional code is partitioned from the structural level down into the \
     Master instance.
   * All component elements of the interface (including clock and reset) are \
     now mapped through the interface boundaries with zero delta delay.
   * The Slave return functions have their own return array. %BR% \
     Each Slave instance must only drive a single return array element and so the \
     other unused elements could have their mode set to 'in' %BR% \
     However, this may result in tool warning messages and user \
     coding guidelines often require all warnings to be cleared or mitigate each \
     in their documentation. The new *null* mode provides an explicit \
     disconnect function for each unused composite element as opposed to the \
     'in' mode as a default.
   * Zero delta delay bus ripping should still be supported by the proposed \
     bidirectional operator (aka the spaceship operator) and also the proposed \
     new *map* subprograms.


---++++ Multi-Master Interface Structure

The diagram below shows a possible multi-master topology for the AMBA AHB-Lite
interface:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_MultiMaster.png" height="522" />

The important thing to note is that it still maintains the previous advantages
by maintaining the decode and multiplexor function blocks inside the interface
controller.

   * In the simple master/slave topology, the master instance is the interface controller.
   * In the multi-master topology, the arbiter instance takes on this role and includes the extra master multiplexor block.

Importantly, their is no duplication in required functional logic and the top
level is restricted to pure interconnectivity.

A single bus signal means that
all instances have access to all elements (clock and reset importantly) with
zero delta delay.

The top level net list can now be optimized easily by synthesis and/or, place
and route tools.

---+++ The NULL Mode

The *null* mode as described already is shown diagrammatically in the slave mode
view shown below:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_SlaveModeView.png" height="522" />

The diagram shows how mode views are used hierarchically and how the *null* mode
disconnects unused items from the bus interface at the *port/parameter*
interface boundary.

The *null* mode on arrays can be thought of as the mirror image of allowing
*array* slices to be set as *open* on port maps as requested in this proposal:
[[P1076.Partiallyconnectedvectorsonportmap][Partially connected vectors on port map]].

Instead of disconnecting *array* slices externally to the entity (dangling actuals on
interface map), it provides a method to explicitly disconnect *array* slices internally 
in the entity (dangling formals on interface map).

---++++ Example of an 8 bit RAM Slave

The block shows an 1Meg x8 RAM with parity:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLite_RAM1Mx8p.png" height="522" />

In order to accommodate the parity bit(s), we need to expand the AHB data bus
from 32 bits to 36 bits.

Connecting this using views starts to look complex but is built
hierarchically and is well structured. First a diagram of the RAM inputs mode
*view*:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLiteRAMslaveModeViewIP.png" height="522" />

Secondly is the mode *view* structure of the outputs:

<img width="875" alt="" src="%ATTACHURLPATH%/UC_BAH_AMBA_AHBLiteRAMslaveModeViewOP.png" height="522" />



-- %USERSIG{BrentHayhoe - 2016-09-09}%

---+ Comments

%COMMENT%
Attachments
I	Attachment	Action	Size	Date	Who	Comment
png	UC_BAH_AMBA_AHBLite.png	manage	8.9 K	2016-10-09 - 14:50	BrentHahoe	AMBA AHB-Lite Block Diagram
png	UC_BAH_AMBA_AHBLiteRAMslaveModeViewIP.png	manage	23.5 K	2016-10-12 - 18:39	BrentHahoe	AMBA AHD-Lite Slave Mode View Inputs
png	UC_BAH_AMBA_AHBLiteRAMslaveModeViewOP.png	manage	18.7 K	2016-10-12 - 18:40	BrentHahoe	AMBA AHD-Lite Slave Mode View Outputs
png	UC_BAH_AMBA_AHBLite_Master.png	manage	7.7 K	2016-09-08 - 11:02	BrentHahoe	AMBA AHD-Lite Master Interface
png	UC_BAH_AMBA_AHBLite_Modified.png	manage	10.5 K	2016-10-09 - 14:52	BrentHahoe	AMBA AHB-Lite Modified Block Diagram
png	UC_BAH_AMBA_AHBLite_MultiMaster.png	manage	14.4 K	2016-10-09 - 14:56	BrentHahoe	AMBA AHB-Lite Multi-master Modified Block Diagram
png	UC_BAH_AMBA_AHBLite_Multiplexor.png	manage	9.9 K	2016-10-09 - 14:53	BrentHahoe	AMBA AHB-Lite Multiplexor Diagram
png	UC_BAH_AMBA_AHBLite_RAM1Mx8p.png	manage	9.8 K	2016-10-12 - 14:12	BrentHahoe	AMBA AHD-Lite Slave 1Mx8 plus parity RAM block
png	UC_BAH_AMBA_AHBLite_Slave.png	manage	8.4 K	2016-09-08 - 12:18	BrentHahoe	AMBA AHD-Lite Slave Interface
png	UC_BAH_AMBA_AHBLite_SlaveModeView.png	manage	25.5 K	2016-10-12 - 17:29	BrentHahoe	AMBA AHD-Lite Slave Mode View
png	UC_BAH_CPUAMandSEntity.png	manage	126.3 K	2015-09-09 - 19:12	BrentHahoe	RTL CPU bus arbiter, master and slave hierarchy entity.
png	UC_BAH_CPUArbiterArrayAndRecord.png	manage	40.6 K	2015-08-17 - 17:57	BrentHahoe	RTL CPU bus arbiter array and record structure.
png	UC_BAH_CPUArbiterEntity.png	manage	78.5 K	2015-09-09 - 19:13	BrentHahoe	RTL CPU bus arbiter entity.
png	UC_BAH_CPUBusArbiterModeView.png	manage	79.7 K	2015-09-09 - 19:13	BrentHahoe	RTL CPU bus arbiter mode view.
png	UC_BAH_CPUBusMasterModeView.png	manage	88.1 K	2015-09-09 - 19:14	BrentHahoe	RTL CPU bus master mode view.
png	UC_BAH_CPUBusRAMslaveModeViewIP.png	manage	20.9 K	2016-10-12 - 14:55	BrentHahoe	AMBA AHD-Lite Slave 1Mx8 plus parity RAM IP Mode View
png	UC_BAH_CPUBusRecord.png	manage	146.7 K	2015-08-17 - 17:56	BrentHahoe	RTL CPU bus top record structure.
png	UC_BAH_CPUBusSlaveModeView.png	manage	62.2 K	2015-09-09 - 19:14	BrentHahoe	RTL CPU bus slave mode view.
png	UC_BAH_CPUInterfaceTop.png	manage	46.3 K	2015-10-01 - 18:22	BrentHahoe	RTL CPU bus interface top entity hierarchy structure.
png	UC_BAH_CPUMasterEntity.png	manage	90.0 K	2015-09-09 - 19:15	BrentHahoe	RTL CPU bus master entity.
png	UC_BAH_CPUMasterRecord.png	manage	30.3 K	2015-08-17 - 17:55	BrentHahoe	RTL CPU bus master record structure.
png	UC_BAH_CPUMplusSEntity.png	manage	123.4 K	2015-09-09 - 19:16	BrentHahoe	RTL CPU bus master plus slave hierarchy entity.
png	UC_BAH_CPUSlaveArrayAndRecord.png	manage	43.7 K	2015-08-17 - 17:54	BrentHahoe	RTL CPU bus slave record and array structure.
png	UC_BAH_CPUSlaveEntity.png	manage	114.3 K	2015-09-09 - 19:21	BrentHahoe	RTL CPU bus slave entity.
png	UC_BAH_CPUSonlyEntity.png	manage	88.7 K	2015-09-09 - 19:17	BrentHahoe	RTL CPU bus slave only hierarchy entity.
png	UC_BAH_VHDL2008CPUAMandSEntity.png	manage	60.3 K	2015-09-09 - 18:24	BrentHahoe	Current VHDL2008 RTL CPU bus arbiter, master and slave hierarchy entity.
png	UC_BAH_VHDL2008CPUArbiterEntity.png	manage	70.3 K	2015-09-08 - 13:34	BrentHahoe	Current VHDL2008 RTL CPU bus arbiter entity.
png	UC_BAH_VHDL2008CPUInterfaceTop.png	manage	82.5 K	2015-09-07 - 17:39	BrentHahoe	Current VHDL2008 RTL CPU bus interface top entity hierarchy structure.
png	UC_BAH_VHDL2008CPUMasterEntity.png	manage	127.3 K	2015-09-09 - 13:11	BrentHahoe	Current VHDL2008 RTL CPU bus master entity.
png	UC_BAH_VHDL2008CPUMplusSEntity.png	manage	55.1 K	2015-09-09 - 09:35	BrentHahoe	Current VHDL2008 RTL CPU bus master plus slave hierarchy entity.
png	UC_BAH_VHDL2008CPUSlaveEntity.png	manage	44.0 K	2015-09-08 - 11:49	BrentHahoe	Current VHDL2008 RTL CPU bus slave entity.
png	UC_BAH_VHDL2008CPUSonlyEntity.png	manage	35.7 K	2015-09-08 - 19:07	BrentHahoe	Current VHDL2008 RTL CPU bus slave only hierarchy entity.
Topic revision: r1 - 2016-10-13 - 14:43:33 - TWikiGuest
P1076