(r1) SignalPools < P1076

P1076 Web>Vhdl2019CollectedRequirements>SignalPools (revision 1) (raw view)~~EditAttach~~

---+ Signal Pools

<br />%TOC%

---++ Proposal Details
   * Who Updates:Main.KevinCameron
   * Date Proposed:
   * Date Last Updated:
   * Priority:
   * Complexity:
   * Focus:

---+++ Current Situation

The communication schemes in VHDL are essentially wires (aka terminals), signals (a bad abstraction) and shared memory, none of which really work well for model things like RF with anteannas in free space.
---+++ Requirement

A signal pool is an object that contains drivers and receivers (e.g. antennae) where resolution functions are applied seperately for each receiver. I.e. the value of resolved signals is a function of the receiver and all the drivers individually, rather than purely a function of the drivers, e.g. as a receiving antenna recedes from transmitters the received signal (the result of resolution) will diminish althogh the transmission is constant.
---+++ Implementation details

Declare things as "pool" rather than "signal". Resolution function has access to receiver context.
---+++ Code Examples
---++ Use Cases

RF modelling of radio space.
---++ Arguments FOR

Missing capability. Easy to implement.
---++ Arguments AGAINST

---++ General Comments

---++ Supporters

_Add your signature here to indicate your support for the proposal_

Topic revision: r1 - 2020-02-17 - 15:34:38 - TWikiGuest

P1076