(r4) ReadRom < P1076

P1076 Web>Vhdl2019CollectedRequirements>ReadRom (revision 4) (raw view)~~EditAttach~~
---+ File IO for ROM

<br />%TOC%

---++ Proposal Information
   * Current Owner: Main.JimLewis, ...
   * Contributors: Main.JimLewis, Main.PatrickLehmann, ...
   * Date Proposed: 2014-June-19
   * Date Last Updated: 2016-Feb-12
   * Priority: high
   * Complexity:
   * Focus: General, RTL
   * Related Issues: None
   * Competing Issues: None
---++ Requirement Summary

Define File IO for ROM. Implies defining types for the ROM. Need to be able to read binary, hex, and decimal from the file. Support common file types

See ISAC [[http://www.eda.org/isac/IRs-VHDL-2002/IR2113.txt][IR2113]]

---++ Implementation

Define the following in std_logic_1164: 
<verbatim>
 -- define type that is an array of std_ulogic_vector
type MemoryArrayType is array (NATURAL range <>) of std_ulogic_vector ; 
-- Make the type name consistent with other matrix types being proposed

-- Define format of file - maybe just one type?  Not too general - use conversions to support less popular types
type MemoryFormatType is (BINARY, OCTAL, DECIMAL, HEX) ; 
type FileFormatType is (TBD) ; 

-- define function to read valeus of Memory Array Type
function ReadMemory (file F: TEXT; FileFmt : FileFormatType ; MemFmt : MemoryFormatType := TBD) return MemoryArrayType ; 
function ReadMemory ( F: string ;  FileFmt : FileFormatType ; MemFmt : MemoryFormatType := TBD) return MemoryArrayType ;
-- Name the function ReadMemV?  Similar to Verilog -- Main.DavidBishop - 2014-06-26</verbatim>

---++ Comments

I think the bigger problem is that some vendors argue, that file I/O is not synthesizable, even at elaboration time. As<br />long as all std.textio related functions and types are mapped to void or ignored while synthesis, it's not possible to provide<br />an user defined or open source package.

So the question to me is: How can VHDL "dictate" that file I/O is synthesizable at elaboration time?<br />Reading and writing should be possible.

From expericence I can say that one tool I'm working with supports file I/O in Verilog but not in VHDL :(.

-- Main.PatrickLehmann - 2016-02-11
---+++ Arguments Against

---++ Supporters

-- Main.JimLewis - 2014-06-19 - should be in an open source package until we stabilize it.

-- Main.PatrickLehmann - 2016-02-11
Topic revision: r1 - 2020-02-17 - 15:34:37 - TWikiGuest
P1076