TWiki
>
P1076 Web
>
VHDL2017
>
LCS2016_I06
(revision 9) (raw view)
Edit
Attach
---+ Language Change Specification for Repair LRM Example 7.3.2.1 Proposal <table border="1" cellpadding="0" cellspacing="0" id="table1" rules="all"> <tbody> <tr> <td bgcolor="#ffffff" valign="top"> *LCS Number:* </td> <td bgcolor="#ffffff" valign="top">LCS-2016-I06</td> </tr> <tr> <td bgcolor="#edf4f9" valign="top"> *Version:* </td> <td bgcolor="#edf4f9" valign="top">1</td> </tr> <tr> <td bgcolor="#ffffff" valign="top"> *Date:* </td> <td bgcolor="#ffffff" valign="top">Nov-29-2016</td> </tr> <tr> <td bgcolor="#edf4f9" valign="top"> *Status:* </td> <td bgcolor="#edf4f9" valign="top"> </td> </tr> <tr> <td bgcolor="#ffffff" valign="top"> *Author:* </td> <td bgcolor="#ffffff" valign="top">Kevin Jennings</td> </tr> <tr> <td bgcolor="#edf4f9" valign="top"> *Email:* </td> <td bgcolor="#edf4f9" valign="top"> [[http://www.eda-twiki.org/cgi-bin/view.cgi/Main/KevinJennings][KevinJennings]]</td> </tr> <tr> <td bgcolor="#ffffff" valign="top"> *Source Doc:* </td> <td bgcolor="#ffffff" valign="top"> [[Fix2008LRM7321][Repair example in Section 7.3.2.1]]</td> </tr> <tr> <td bgcolor="#edf4f9" valign="top"> *Summary:* </td> <td bgcolor="#edf4f9" valign="top">Repair example in Section 7.3.2.1</td> </tr> </tbody> </table> ---+++ Voting Results: Cast your votes here Yes: 1 %USERSIG{KevinJennings - 2016-11-29}% 1 %USERSIG{RyanHinton - 2016-12-19}% 1 %USERSIG{ThomasPreusser - 2016-12-27}% 1 %USERSIG{MartinZabel - 2017-01-19}% 1 %USERSIG{JimLeiws - 2017-02-06}% 1 %USERSIG{PatrickLehmann - 2017-02-06}% - ver 1 No: 1 Abstain: 1 %USERSIG{MartinThompson - 2016-12-12}% 1. %USERSIG{BrentHahoe - 2017-02-16}% Version 1 - Abstain due to lack of personal time for review. ---+++ Details of Language Change: Key: * Existing LRM text is shown in BLACK font * Additional LRM text is shown in %RED%<u>RED and underlined</u>%ENDCOLOR% * Deleted LRM text is shown in <del>RED with strike-through</del> <p> </p> ---++++ LRM 7.3.2.1 page 100 near bottom *entity* AND_GATE <b>is</b><br /><b>generic</b> (I1toO, I2toO: DELAY_LENGTH := 4 ns);<br /><b>port</b> (I1, I2: in BIT %RED%<b><u>:= '1'</u></b>%ENDCOLOR%; O: out BIT);<br /><b>end entity</b> AND_GATE; ---++++ LRM 7.3.2.1 page 100 near bottom *component* AND_GATE <b>is</b><br /><b>generic</b> %RED%<b><u>(</u></b>%ENDCOLOR% I1toO, I2toO: DELAY_LENGTH := 4 ns);<br /><b>port</b> (I1, I2: in BIT %RED%<b><u>:= '1'</u></b>%ENDCOLOR%; O: out BIT);<br /><b>end component </b>AND_GATE; ---+++++ Comments Hopefully it will save someone else time to know that the initial value is needed because it is left open in the configuration of L2 in the declarative region of Half_Adder.Structure. -- %BUBBLESIG{RyanHinton - 2016-12-19}%<br />%COMMENT%
Edit
|
Attach
|
P
rint version
|
H
istory
:
r14
|
r11
<
r10
<
r9
<
r8
|
B
acklinks
|
V
iew topic
|
Raw edit
|
More topic actions...
Topic revision: r1 - 2017-04-02 - 16:19:58 -
TWikiGuest
P1076
Log In
or
Register
P1076 Web
Create New Topic
Index
Search
Changes
Notifications
RSS Feed
Statistics
Preferences
Webs
Main
P1076
Ballots
LCS2016_080
P10761
P1647
P16661
P1685
P1734
P1735
P1778
P1800
P1801
Sandbox
TWiki
VIP
VerilogAMS
Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki?
Send feedback