(r6) InterfaceWhiteboard < P1076

P1076 Web>Vhdl2019CollectedRequirements>Whiteboards>InterfaceWhiteboard (revision 6) (raw view)~~EditAttach~~

---+ Interface Discussions

Pages for the bullet points and questions relating to various aspects of the proposed new *Interface* construct.

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[[HeterogeneousInterfaceRequirements][Heterogeneous Interface Requirements]]

A basic set of requirements as originally set down in the whitepaper attached to Ernst's Proposal [[HeterogeneousInterfaces][HERE]].

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[[InterfaceConcepts][Interface Mode Requirements]]

Requirements relating to port/parameter mode extensions required for a simple CPU master/slave(s) interface example.

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[[InterfaceBundles][Interface Bundle Requirements]]

Requirements relating to bundling of types and objects for interfaces.

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[[SVInterfaces][Overview of SystemVerilog Interfaces]]

Includes thoughts how the functionality relates to VHDL concepts.

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[[AdditionalInterfaceProposals][Additional required proposals]]

Additional existing proposals to be incorporated with the new Interface Construct.

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[[BundlesInVHDL][Bundles in VHDL]]

Discussion of issues around defining a concept of a *bundle* (or *interface*) in VHDL

   * [[BrentHayhoeSimpleRecordBasedBundle][Brent Hayhoe Comment: Simple Record Form of Bundle Usage]]
   * [[DanielKhoSimpleRecordBasedBundle][Daniel Kho Comment: Options for using generics with Bundles]]

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[[MovingForward][Status Quo and Moving Forward]]

Summing up of where we are and how to proceed further.

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[[InterfaceAcceptedRequirements][Accepted requirements from WG meetings]]

Collection of definitive requirements for an *interface* construct and specifying a *bundle*.

Topic revision: r1 - 2015-07-17 - 11:05:44 - TWikiGuest

P1076