(r15) InterfaceAcceptedRequirements < P1076

P1076 Web>Vhdl2019CollectedRequirements>Whiteboards>InterfaceWhiteboard>InterfaceAcceptedRequirements (revision 15) (raw view)~~EditAttach~~
---+ *Interface* and *Bundle* Requirements

%TOC%

---++ Accepted Requirements (draft)

The *interface* construct was originally prompted by the requirement for better support in order to enhance/solve the directional *record* problem encountered by engineers trying to simplify and improve structural interconnects between *entity* instantiations.

   1 RTL Requirements- Light Weight - 
      1 Must be synthesis capable
      1 Composite/Collection of objects 
         * *signal* - required
      1 Create by declation, instantiation, ...
      1 Method to access elements/subelements that is independent of method or location of declaration
      1 Declare / specify on entity interface or subprogram interface
      1 Associate/Map on entity instance or subprogram call
      1 ?Generics
      1 Method for sizing unconstrained elements
      1 ?Support Shared Globals (Clk, Reset, ...) - similar to SV interfaces 
         1 How do we handle globals like clk and reset? How does this impact events?
      1 Events - do we care whether events are on individual objects or as a composite 
         1 What does event mean if the object is out mode?
         1 What about a collection of clocks?
         1 What about a collection of busses?
      1 Assignment to entire collection? TBD 
         1 What if modes/directions are not all out or inout
         1 Would need use cases to validate if all out or inout is useful
         1 ?No because then a record could be used instead
      1 Composition 
         1 Collecting other collections
         1 Collecting other modes
         1 ?Shared Globals (Clk, reset, ...)
      1 Access Control / Decomposition - similar to !ModPort 
         1 Direction control of objects
         1 support conjugate and monitor (all in) capability (via attribute or other)
         1 ?Shared Globals (Clk, reset, ...)
         1 ??Access to Subprograms
         1 ??Exclusion of objects
         1 Must support a access control/Decomposition declaration/specification
         1 ?Can access control happen directly on interface?
      1 Decomposition within a program (architecture / procedure) 
         1 Assign to items of the collection
         1 Read individual items of the collection
      1 ??Subprograms
   1 *Behavioral Requirements* 
      1 Composite/Collection of objects 
         * *signal* - required
         * *shared variable* - required (???regular variables???)
         * *constant* - ???
         * *file* - ???
         * *terminal* - required - (VHDL-AMS)
         * *quantity* - required - (VHDL-AMS)
         * *bundle* - required
      1 Create by declation, instantiation, ...
      1 Method to access elements/subelements that is independent of method or location of declaration
      1 Declare / specify on entity interface or subprogram interface
      1 Associate/Map on entity instance or subprogram call
      1 Support Generics
      1 Method for sizing unconstrained elements
      1 Support Shared Globals (Clk, Reset, ...) - similar to SV interfaces 
         1 How to handle globals like clk and reset?
      1 Events - want events on individual objects 
         1 What does event mean if the object is out mode?
         1 What about a collection of clocks?
         1 What about a collection of busses?
      1 Assignment? Only to elements within the collection
      1 Composition 
         1 Collecting other collections
         1 Collecting other modes
         1 Shared Globals
      1 Access Control / Decomposition - similar to !ModPort 
         1 Directions of objects
         1 support conjugate and monitor (all in) capability (via attribute or other)
         1 ?Shared Globals (Clk, reset, ...)
         1 ?Access to Subprograms
         1 ???Import/Export of subprograms - big change - 
            1 impure subprograms need to access ports of a local entity
         1 Exclusion of objects
         1 Must support a access control/Decomposition declaration/specification
         1 ?Can access control happen directly on interface?
      1 Decomposition within a program (architecture / procedure) 
         1 Assign to items of the collection
         1 Read individual items of the collection
      1 Subprograms 
         1 access interface internals
      1 Avoid compiler issues when integrating <br />port ( A : !MyMode !MyType) ; -- VHDL already has this in some areas.<br /> port ( A : &lt;MyMode&gt; !MyType) ; -- A fix, but there are many variations<br /> port ( A : !MyType(!MyMode)) ; -- A fix, but there are many variations
      1 Internal to a model, use an identifier to dynamically associate with one of 2 identical interfaces
      1 Virtual Interface 
         1 Change interface instance
         1 Dynamically plug in a different testbench
---+++ Use Cases

   1 [[UCInterfaceDocPreface][Interface.doc 1.0.: Preface]]
   1 [[UCInterfaceDocIntroduction][Interface.doc 2.0.: Introduction]]
   1 [[UCInterfaceDocTransBasedTB][Interface,doc 3.1.: Transaction Based Testbench]]
   1 [[UCInterfaceDocRTLBundles][Interface.doc 3.2.: RTL Bundles]]
   1 [[UCInterfaceDocRTLSimpleIF][Interface.doc 3.2.: RTL Simple Interface]]
   1 [[UCInterfaceDocCurrentCapab][Interface.doc 4.0.: Current Capabilities]]
   1 [[UCInterfaceDocImplemConsider][Interface.doc 5.0.: Implementation Considerations]]
   1 [[UCInterfaceDocInterfaceImplem][Interface.doc 6.0.: Interface Implementation]]
   1 [[UCInterfaceDocHistoricDiscuss][Interface.doc 7.0.: Historical Discussion]]
   1 [[UCProposalBlockInterfaces][Proposal: Records with Directional Subtypes]]
   1 [[UCProposalNewBusModeForBidirectionalPortSignals][Proposal: "Bus" port mode for bidirectional port signals]]
   1 [[UCProposalInterfaceConstructandPortModeConfigurations][Proposal: Interface Construct and Port Mode Configurations]]
   1 [[UCProposalPackageAsInterface][Proposal: Packages as an Interface Construct]]
   1 [[UCIR2067LogicalLinkInterfaceAbstraction][IR2067: Logical link interface abstraction]]
   1 [[UCIR2089DirectionalRecords][IR2089: Directional Records]]
   1 [[UCVHDL200xFT17CompositeInterfaceMode][VHDL-200x FT17: Composite interface mode]]
   1 [[P1076.UCMinimalRTLSignalInterface][Use Case: Minimal RTL Signal Based Interface]]

---++ Delete the following after review of the above Accepted list:

---++ [[HeterogeneousInterfaceRequirements][Heterogeneous Interface Requirements]]

---++ WG Minuted Requirements

   * [[2015_MeetingMay14][WG meeting - 14 May 2015:]]
   * [[2015_MeetingMay28][WG meeting - 28 May 2015:]]
   * [[2015_MeetingJune11][WG meeting - 11 June 2015:]]
   * [[2015_MeetingJuly9][WG meeting - 9 July 2015:]]

WG meeting - 9 July 2015:

   * Requirement: Bundles 
      * Drivers
      * Individual Directions
      * Hierarchical composability
      * Events: on separate elements / subelements
      * Objects in a bundle: Signals, Shared Variables, AMS ...
      * Views of connection to bundle - simlar to ModPort
Topic revision: r1 - 2015-08-09 - 22:41:58 - TWikiGuest
P1076