TWiki
>
P1076 Web
>
Vhdl2019CollectedRequirements
>
ExtendedHwFunctions
(revision 1) (raw view)
Edit
Attach
---+ Extended Hardware functions like mux, decoders, adders <br />%TOC% ---++ Proposal Editing Information * Who Updates: * Date Proposed: * Date Last Updated: * Priority: * Complexity: * Focus: Testbench ---++ Requirement Summary * Simplify Creation of RTL macros (Also interested: Main.MartinThompson, Main.DanielKho): * Library of standard functions * Mux2, what else? * To what use, Jim says behavior, David K. suggests mixed level of abstraction, retargetting * Syntax based flip-flop extensions are here: [[ClockedShorthand]] See also: [[MeetingDecember15][Dec 15, 2011]] and [[MeetingMarch31][Mar 31, 2011]] ---++ Proposal Recommend that we forward this to the open source package working group for implementation separate of the VHDL standard. Create hardware with procedure and function calls. For example, use a procedure for a flip-flop: Reg(Clk, D, Q) ; RegPipe (Clk, D, Q, 5) ; -- adds a 5 deep pipelining / shift register. ---++ Rationale ---++ Related and/or Competing Issues: None ---++ Use Model: ---++ Questions ---++ General Comments The open source and vendor independet IP core library [[https://github.com/VLSI-EDA/PoC][PoC]] comes with several syntheziable functions.<br />Examples for one-liners: * a D-FF in standard VHDL<br /><span class="WYSIWYG_TT">mySignal_reg <= mySignal when rising_edge(Clock);</span> * a D-FF with enable and reset, as well as a reset value (INIT)<br /><span class="WYSIWYG_TT">mySignal_reg <= ffdre(q => mySignal_reg, d => mySignal, en => enable, rst => reset, INIT => '1') when rising_edge(Clock);</span> * an optional output register<br /><span class="WYSIWYG_TT">output <= output_i when registered(Clock, IS_REGISTERED);</span> * Encoding conversion<br /><span class="WYSIWYG_TT">gray <= bin2gray(Counter);</span><br /><span class="WYSIWYG_TT">onehot <= bin2onehot(Counter);</span> Source: [[https://github.com/VLSI-EDA/PoC/blob/master/src/common/components.vhdl][PoC.components]] and [[https://github.com/VLSI-EDA/PoC/blob/master/src/common/utils.vhdl][PoC.utils]] -- Main.PatrickLehmann - 2016-02- ---++ Supporters _Add your signature here to indicate your support for the proposal_ <em>-- Main.MartinThompson - 2013-02-22<br /></em> -- Main.PatrickLehmann - 2016-02-19
Edit
|
Attach
|
P
rint version
|
H
istory
:
r5
|
r4
<
r3
<
r2
<
r1
|
B
acklinks
|
V
iew topic
|
Raw edit
|
More topic actions...
Topic revision: r1 - 2020-02-17 - 15:34:30 -
TWikiGuest
P1076
Log In
or
Register
P1076 Web
Create New Topic
Index
Search
Changes
Notifications
RSS Feed
Statistics
Preferences
Webs
Main
P1076
Ballots
LCS2016_080
P10761
P1647
P16661
P1685
P1734
P1735
P1778
P1800
P1801
Sandbox
TWiki
VIP
VerilogAMS
Copyright © 2008-2025 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki?
Send feedback