ExpressionsAndSignalParameters < P1076

P1076 Web>VHDLProposals>ExpressionsAndSignalParameters (2020-10-30, JimLewis) (raw view)EditAttach

---+ Mapping Expressions to Signal Parameters

%TOC%

---++ Proposal Information
   * Current Owner: Main.JimLewis, ...
   * Contributors: Main.JimLewis, ...
   * Date Proposed: 2014-June-22
   * Date Last Updated: 2020-October-30
   * Priority:
   * Complexity:
   * Focus: Testbench
   * Related Issues: loosely, but both are useful [[WaitLevel] [Wait Level - Syntax Solution] ] 
   * Competing Issues: None
---++ Requirement Summary

Mapping Expressions to Signal Parameters.

One application is to provide a code based solution to Level Sensitive Wait

See also [[WaitLevel] [Wait Level - Syntax Solution] ] 
---++ A Code Solution

This can easily be accomplished with the code
<verbatim>
if A /= Level then
  wait until A = Level ;
end if; </verbatim>

However, what is being sought is a more concise solution.

---++ Encapsulation with a Procedure

If the following worked, it would be an acceptable solution. However while a signal input to an entity allows expressions with VHDL-2008, a signal input to a parameter of a subprogram does not.
<verbatim>procedure WaitLevel (
  signal condition : in boolean 
) is 
begin
  if not condition then
    wait until condition ;
  end if ; 
end procedure WaitLevel ; </verbatim>

General support issues: When an expression is passed as input signal parameter, it would have the default value of the type (here false) until a delta cycle passes. Here that works just fine.


---++ Comments


---+++ Arguments Against

---++ Supporters

Topic revision: r1 - 2020-10-30 - 16:17:55 - JimLewis

P1076