(r1) UCComplexRTLSignalCPUInterfaceAHBLcodeMod < P1076/Ballots

P1076/Ballots Web>CollectedRequirements>P1076BallotsInterfaceAndBundleEnhancements>UCComplexRTLSignalCPUInterface>UCComplexRTLSignalCPUInterfaceAHBLcodeMod (revision 1) (raw view)~~EditAttach~~
---+!! AHB-Lite Modified Interface

%TOC%

---++ Example Code

<sticky><pre>%BLACK%
   -------------------------------------------
   -- Support Package for AHB-Lite Protocol --
   -------------------------------------------
   <b>library</b> ieee;
   <b>context</b> ieee.ieee_std_context;

   <b>package</b> amba_ahbl_pkg
      <b>generic</b>(
         slaves_max_jg : positive := 3
      );
      <b>is</b>
      <b>constant</b> slaves_total_jc    : positive := slaves_max_jg;     -- individual slaves
      <b>subtype</b>  slaves_total_jrt  <b>is</b> natural <b>range</b> slaves_total_jc <b>downto</b> 1;

      -- AHBL Slave Select bus
      <b>subtype</b>  HSEL_vst          <b>is</b> std_logic_vector(slaves_total_jrt);

      -- AHBL Address bus
      <b>constant</b> HADDR_width_jc     : positive := 32;
      <b>subtype</b>  HADDR_jrt         <b>is</b> natural <b>range</b> HADDR_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HADDR_vst         <b>is</b> std_logic_vector(HADDR_jrt);

      -- AHBL Size control
      <b>constant</b> HSIZE_width_jc     : positive := 3;
      <b>subtype</b>  HSIZE_jrt         <b>is</b> natural <b>range</b> HSIZE_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HSIZE_vst         <b>is</b> std_logic_vector(HSIZE_jrt);

      -- AHBL Burst control
      <b>constant</b> HBURST_width_jc     : positive := 3;
      <b>subtype</b>  HBURST_jrt         <b>is</b> natural <b>range</b> HBURST_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HBURST_vst         <b>is</b> std_logic_vector(HBURST_jrt);

      -- AHBL Protection control
      <b>constant</b> HPROT_width_jc     : positive := 4;
      <b>subtype</b>  HPROT_jrt         <b>is</b> natural <b>range</b> HPROT_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HPROT_vst         <b>is</b> std_logic_vector(HPROT_jrt);

      -- AHBL Transfer Type control
      <b>constant</b> HTRANS_width_jc     : positive := 2;
      <b>subtype</b>  HTRANS_jrt         <b>is</b> natural <b>range</b> HTRANS_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HTRANS_vst         <b>is</b> std_logic_vector(HTRANS_jrt);

      -- AHBL Data bus
      <b>constant</b> HDATA_width_jc     : positive := 32;
      <b>subtype</b>  HDATA_jrt         <b>is</b> natural <b>range</b> HDATA_width_jc- 1 <b>downto</b> 0;
      <b>subtype</b>  HDATA_vst         <b>is</b> std_logic_vector(HDATA_jrt);

      -----------------------------------------------------
      -- Record & Array Types for AMBA AHB-Lite Protocol --
      -----------------------------------------------------
      -- Slave record for AMBA AHB-Lite bus
      <b>type</b> s_amba_ahb_rt <b>is</b> -- AMBA AHBL slave return record
         <b>record</b>
            HREADYOUT_l : std_logic;     -- AHBL transfer complete
            HRESP_l     : std_logic;     -- AHBL transfer response
            HRDATA_vl   : HDATA_vst;     -- AHBL read data bus (32bit)
         <b>end record</b> s_amba_ahb_rt;

      -- Slave array for AMBA AHB-Lite bus
      <b>type</b> s_amba_ahb_at <b>is</b>
         <b>array</b>(slaves_total_jrt)
            <b>of</b> s_amba_ahb_rt;             -- Array of slave return records

      -- Master record for AMBA AHB-Lite bus
      <b>type</b> m_amba_ahb_rt <b>is</b> -- AMBA AHBL master record
         <b>record</b>
            HRESET_nl   : std_logic;     -- AHBL global reset
            HCLK_l      : std_logic;     -- AHBL global clock

            HREADY_l    : std_logic;     -- AHBL transfer complete
            HADDR_vl    : HADDR_vst;     -- AHBL address bus (32bit)
            HWRITE_l    : std_logic;     -- AHBL transfer write/read control
            HSIZE_vl    : HSIZE_vst;     -- AHBL transfer size control (3bit)
            HBURST_vl   : HBURST_vst;    -- AHBL transfer burst control (3bit)
            HPROT_vl    : HPROT_vst;     -- AHBL access protection control (4bit)
            HTRANS_vl   : HTRANS_vst;    -- AHBL transfer type control (2bit)
            HMASTLOCK_l : std_logic;     -- AHBL locked transfer control
            HWDATA_vl   : HDATA_vst;     -- AHBL write data bus (32bit)
         <b>end record</b> m_amba_ahb_rt;

      -- Top record for AMBA AHB-Lite bus
      <b>type</b> amba_ahb_rt <b>is</b>  -- AMBA AHBL top record record
         <b>record</b>
            HSEL_vl       : HSEL_vst;      -- AHBL slave select vector
            s_amba_ahb_al : s_amba_ahb_at; -- AHBL slave return array
            m_amba_ahb_rl : m_amba_ahb_rt; -- AHBL master record
         <b>end record</b> amba_ahb_rt;

      --------------------------------------------------------
      -- Record & Array Mode Views for AHBL Composite Types --
      --------------------------------------------------------
      -- Slave array mode view
      <b>array view</b> s_amba_ahb_avw <b>of</b> s_amba_ahb_at <b>is</b>
         <b>generic</b>(
            HSEL_id_jg : slaves_total_jrt
         );
         <b>element</b>(
            HSEL_id_jg : <b>out</b>  s_amba_ahb_rt;
            <b>others</b>     : <b>null</b> s_amba_ahb_rt
         );
      <b>end array view</b> s_slave_avw;

      -- Master record mode view
      <b>record view</b> m_amba_ahb_rvw <b>of</b> m_amba_ahb_rt <b>is</b>
         <b>element</b>(
            HRESET_nl   : <b>in</b>     std_logic;
            HCLK_l      : <b>in</b>     std_logic;

            HREADY_l    : <b>out</b>    std_logic;
            HADDR_vl    : <b>out</b>    HADDR_vst;
            HWRITE_l    : <b>out</b>    std_logic;
            HSIZE_vl    : <b>out</b>    HSIZE_vst;
            HBURST_vl   : <b>out</b>    HBURST_vst;
            HPROT_vl    : <b>out</b>    HPROT_vst;
            HTRANS_vl   : <b>out</b>    HTRANS_vst;
            HMASTLOCK_l : <b>out</b>    std_logic;
            HRDATA_vl   : <b>out</b>    HDATA_vst;
         );
      <b>end record view</b> m_amba_ahb_rvw;

      -- AMBA AHB-Lite slave record mode view
      <b>record view</b> amba_ahb_slave_rvw <b>of</b> amba_ahb_rt <b>is</b>
         <b>generic</b>(
            slave_id_jg : slaves_total_jrt
         );
         <b>element</b>(
            HSEL_vl       : <b>in</b>       HSEL_vst;
            s_amba_ahb_al : <b>view</b>     s_amba_ahb_at(s_amba_ahb_avw(HSEL_id_jg => slave_id_jg));
            m_amba_ahb_rl : <b>in</b>       m_amba_ahb_rt;
         );
      <b>end record view</b> amba_ahb_slave_rvw;

      -- AMBA AHB-Lite master record mode view
      <b>record view</b> amba_ahb_master_rvw <b>of</b> amba_ahb_rt <b>is</b>
         <b>element</b>(
            HSEL_vl       : <b>out</b>      HSEL_vst;
            s_amba_ahb_al : <b>in</b>       s_amba_ahb_at;
            m_amba_ahb_rl : <b>view</b>     m_amba_ahb_rt(m_amba_ahb_rvw);
         );
      <b>end record view</b> amba_ahb_master_rvw;

      -----------------------------------------
      -- Decoder and Multiplexor Subprograms --
      -----------------------------------------
      -- Slave select decoder function
      <b>function</b> HSEL_decoder_f(;
            m_amba_ahb_ri : m_amba_ahb_rt
         ) <b>return</b> HSEL_vst;

      -- Slave return multiplexor function
      <b>function</b> slave_multiplexor_f(;
            amba_ahb_ri : amba_ahb_rt
         ) <b>return</b> s_amba_ahb_rt;

      --------------------------------
      -- Context Clause for Package --
      --------------------------------
      <b>context</b> amba_ahbl_context;
         <b>library</b> ieee;
         <b>context</b> ieee.ieee_std_context;
            <b>use work</b>.amba_ahbl_pkg.all;
      <b>end context</b> amba_ahbl_context;
   <b>end package</b> amba_ahbl_pkg;

   -- A package body is required to define the decoder and multiplexor
   -- functions.
   <b>package body</b> amba_ahbl_pkg;
      -----------------------------------------
      -- Decoder and Multiplexor Subprograms --
      -----------------------------------------
      -- Slave select decoder function
      <b>function</b> HSEL_decoder_f(;
            m_amba_ahb_ri : m_amba_ahb_rt
         ) <b>return</b> HSEL_vst <b>is</b>
         <b>variable</b> HSEL_vv : HSEL_vst;
      <b>begin</b>
         ...
         <b>return</b> HSEL_vv;
      <b>end function</b> HSEL_decoder_f;

      -- Slave return multiplexor function
      <b>function</b> slave_multiplexor_f(;
            amba_ahb_ri : amba_ahb_rt
         ) <b>return</b> s_amba_ahb_rt <b>is</b>
         <b>variable</b> s_amba_ahb_rv : s_amba_ahb_rt;
      <b>begin</b>
         ...
         <b>return</b> s_amba_ahb_rv;
      <b>end function</b> HSEL_decode_f;
   <b>end package body</b> amba_ahbl_pkg;

   -----------------------------------------------------------------
   -- Declare entities for AHBL Master, Slave and top-level Block --
   -----------------------------------------------------------------
   -- AHB-Lite Master Entity
   <b>context work</b>.amba_ahbl_context;
   <b>entity</b> ahbl_master_ent <b>is</b>(
      <b>port</b>(
         amba_ahb_rif : <b>view</b> amba_ahb_rt(amba_ahb_master_rvw)
      );
   <b>end entity</b> ahbl_master_ent;
   <b>architecture</b> rtl_arch <b>of</b> ahbl_master_ent <b>is</b>
      <b>signal</b> s_amba_ahb_rs : s_amba_ahb_rt;
   <b>begin</b>(
      -- Slave Decoder now internal to master instance
      HSEL_decoder_asgn :
         amba_ahb_rif.HSEL_vl <= HSEL_decoder_f(amba_ahb_rif);

      -- Slave Multiplexor now internal to master instance
      slave_multiplexor_asgn :
         s_amba_ahb_rs <= slave_multiplexor_f(amba_ahb_rif);

      -- HREADY decode
      HREADY_asgn :
         amba_ahb_rif.m_amba_ahb_rl.HREADY_l <= s_amba_ahb_rs.HREADYOUT_l;
     ....
   <b>end architecture</b> rtl_arch;</b>

   -- AHB-Lite Slave Entity
   <b>context work</b>.amba_ahbl_context;
   <b>entity</b> ahbl_slave_ent <b>is</b>(
      <b>generic</b>(
         inst_id_jg : positive
      );
      <b>port</b>(
         amba_ahb_rif : <b>view</b> amba_ahb_rt(amba_ahb_slave_rvw(slave_id_jg => inst_id_jg))
      );
   <b>end entity</b> ahbl_slave_ent;
   <b>architecture</b> rtl_arch <b>of</b> ahbl_slave_ent <b>is</b>
      -- Slave Decoder
      <b>alias</b> HSEL_s : std_logic <b>is</b> amba_ahb_rif.HSEL_vl(inst_id_jg);
      -- Slave multiplexor return
      <b>alias</b> s_amba_ahb_rs : s_amba_ahb_rt <b>is</b> amba_ahb_rif.s_amba_ahb_al(inst_id_jg);
   <b>begin</b>(
      ....
   <b>end architecture</b> rtl_arch;</b>

   ---------------
   -- Top Level --
   ---------------
   -- Top-level AHB-Lite Block Structure
   <b>context work</b>.amba_ahbl_context;
   <b>entity</b> ahbl_block_ent <b>is</b>(
   <b>end entity</b> ahbl_block_ent;

   <b>architecture</b> rtl_arch <b>of</b> ahbl_block_ent <b>is</b>
      <b>signal</b> amba_ahb_rs : amba_ahb_rt;
   <b>begin</b>(

      -- Clock and Reset Control for AHB-Lite Block
      clk_and_rst_inst : <b>entity</b> clk_and_rst_ent(rtl_arch)
         <b>port map</b>(
            rst_o => amba_ahb_rs.m_amba_ahb_rl.HRESET_nl,
            clk_o => amba_ahb_rs.m_amba_ahb_rl.HCLK_i
         );

      -- Master Instantiation for AHB-Lite Block
      ahbl_master_inst : <b>entity</b> ahbl_master_ent(rtl_arch)
         <b>port map</b>(
            amba_ahb_rif => amba_ahb_rs
         );

      -- Slave Instantiations for AHB-Lite Block
      ahbl_slave_gen : <b>for</b> i_jlv <b>in</b> slaves_total_jrt
         <b>generate</b>
         ahbl_slave_inst : <b>entity</b> ahbl_slave_ent(rtl_arch)
            <b>generic map</b>(
               inst_id_jg => i_jlv,
            )
            <b>port map</b>(
               amba_ahb_rif => amba_ahb_rif
            );
      <b>end generate</b>;
   <b>end architecture</b> rtl_arch;
%ENDCOLOR%</pre></sticky>

---++ Interface Connections

| *Control Instance:* ||
| clk_and_rst_inst    ||
| *Name*              | *I/O Element*                                                 | *Mode*        | *Composite Signal or Element* |
| <b>HRESETn</b>      | rst_o                                                         | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HRESET_nl |
| <b>HCLK</b>         | clk_o                                                         | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HCLK_l |
| ||||
| *Master Instance:*  ||
| ahbl_master_inst    ||
| *Name*              | *I/O Element*                                                 | *Mode*        | *Composite Signal or Element* |
| array of %BR% \
  <b>HSEL</b>         | %BR% \
amba_ahb_rif.HSEL_vl(3 downto 1)                                                      | %BR% \
<b>out</b>                                                                                            | %BR% \
amba_ahb_rs.HSEL_vl(3 downto 1)                                                                                                       |
| ||||
| array of %BR% \
  <b>HREADYOUT</b>    | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HREADYOUT_l                                    | %BR% \
<b>in</b>                                                                                              | %BR% \
amba_ahb_rs.s_amba_ahb_al(3 downto 1).HREADYOUT_l                                                                                     |
| array of %BR% \
  <b>HRESP</b>        | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HRESP_l                                        | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rs.s_amba_ahb_al(3 downto 1).HRESP_l                                                                                         |
| array of %BR% \
  <b>HRDATA[31:0]</b> | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HRDATA_vl(31 downto 0)                          | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rs.s_amba_ahb_al(3 downto 1).HRDATA_vl(31 downto 0)                                                                          |
| ||||
| <b>HRESETn</b>      | amba_ahb_rif.m_amba_ahb_rl.HRESET_nl                          | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HRESET_nl |
| <b>HCLK</b>         | amba_ahb_rif.m_amba_ahb_rl.HCLK_l                             | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HCLK_l |
| <b>HREADY</b>       | amba_ahb_rif.m_amba_ahb_rl.HREADY_l                           | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | amba_ahb_rif.m_amba_ahb_rl.HWRITE_l                           | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HWRITE_l |
| <b>HSIZE[2:0]</b>   | amba_ahb_rif.m_amba_ahb_rl.HSIZE_vl(2 downto 0)               | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | amba_ahb_rif.m_amba_ahb_rl.HBURST_vl(2 downto 0)              | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | amba_ahb_rif.m_amba_ahb_rl.HPROT_vl(3 downto 0)               | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | amba_ahb_rif.m_amba_ahb_rl.HTRANS_vl(1 downto 0)              | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | amba_ahb_rif.m_amba_ahb_rl.HMASTLOCK_l                        | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | amba_ahb_rif.m_amba_ahb_rl.HWDATA_vl(31 downto 0)             | <b>out</b>    | amba_ahb_rs.m_amba_ahb_rl.HWDATA_vl(31 downto 0) |
| ||||
| *Slave Instances:*  ||
| ahbl_slavex_gen(x).ahbl_slave_inst ||
| *Name*              | *I/O Element*                                                 | *Mode*        | *Composite Signal or Element* |
| array of %BR% \
  <b>HSEL</b>         | amba_ahb_rif.HSEL_vl(x) %BR% \
amba_ahb_rif.HSEL_vl(<b>others</b>)                                                   | <b>in</b> %BR% \
<b>in</b>                                                                                             | amba_ahb_rs.HSEL_vl(x) %BR% \
amba_ahb_rs.HSEL_vl(<b>others</b>)                                                                                                    |
| ||||
| array of %BR% \
  <b>HREADYOUT</b>    | amba_ahb_rif.s_amba_ahb_al(x).HREADYOUT_l %BR% \
amba_ahb_rif.s_amba_ahb_al(<b>others</b>).HREADYOUT_l                                 | <b>out</b> %BR% \
<b>in</b>                                                                                             | amba_ahb_rs.s_amba_ahb_al(x).HREADYOUT_l %BR% \
amba_ahb_rs.s_amba_ahb_al(<b>others</b>).HREADYOUT_l                                                                                  |
| array of %BR% \
  <b>HRESP</b>        | amba_ahb_rif.s_amba_ahb_al(x).HRESP_l %BR% \
amba_ahb_rif.s_amba_ahb_al(<b>others</b>).HRESP_l                                     | <b>out</b> %BR% \
<b>in</b>                                                                                             | amba_ahb_rs.s_amba_ahb_al(x).HRESP_l %BR% \
amba_ahb_rs.s_amba_ahb_al(<b>others</b>).HRESP_l                                                                                      |
| array of %BR% \
  <b>HRDATA[31:0]</b> | amba_ahb_rif.s_amba_ahb_al(x).HRDATA_vl(31 downto 0) %BR% \
amba_ahb_rif.s_amba_ahb_al(<b>others</b>).HRDATA_vl(31 downto 0)                      | <b>out</b> %BR% \
<b>in</b>                                                                                             | amba_ahb_rs.s_amba_ahb_al(x).HRDATA_vl(31 downto 0) %BR% \
amba_ahb_rs.s_amba_ahb_al(<b>others</b>).HRDATA_vl(31 downto 0)                                                                       |
| ||||
| <b>HRESETn</b>      | amba_ahb_rif.m_amba_ahb_rl.HRESET_nl                          | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HRESET_nl |
| <b>HCLK</b>         | amba_ahb_rif.m_amba_ahb_rl.HCLK_l                             | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HCLK_l |
| <b>HREADY</b>       | amba_ahb_rif.m_amba_ahb_rl.HREADY_l                           | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HREADY_l |
| <b>HADDR[31:0]</b>  | amba_ahb_rif.m_amba_ahb_rl.HADDR_vl(31 downto 0)              | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | amba_ahb_rif.m_amba_ahb_rl.HWRITE_l                           | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HWRITE_l |
| <b>HSIZE[2:0]</b>   | amba_ahb_rif.m_amba_ahb_rl.HSIZE_vl(2 downto 0)               | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | amba_ahb_rif.m_amba_ahb_rl.HBURST_vl(2 downto 0)              | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | amba_ahb_rif.m_amba_ahb_rl.HPROT_vl(3 downto 0)               | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | amba_ahb_rif.m_amba_ahb_rl.HTRANS_vl(1 downto 0)              | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | amba_ahb_rif.m_amba_ahb_rl.HMASTLOCK_l                        | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | amba_ahb_rif.m_amba_ahb_rl.HWDATA_vl(31 downto 0)             | <b>in</b>     | amba_ahb_rs.m_amba_ahb_rl.HWDATA_vl(31 downto 0) |
| ||||
| *Decoder Function:* ||
| ahbl_master_inst.HSEL_decoder_asgn ||
| *Name*              | *Input Element*                                               | *Mode*        | *Composite Signal or Element* |
| array of %BR% \
  <b>HSEL</b>         | %BR% \
amba_ahb_ri.HSEL_vl(3 downto 1)                                                       | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.HSEL_vl(3 downto 1)                                                                              |
| ||||
| array of %BR% \
  <b>HREADYOUT</b>    | %BR% \
amba_ahb_ri.s_amba_ahb_al(3 downto 1).HREADYOUT_l                                     | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HREADYOUT_l                                                            |
| array of %BR% \
  <b>HRESP</b>        | %BR% \
amba_ahb_ri.s_amba_ahb_al(3 downto 1).HRESP_l                                         | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HRESP_l                                                                |
| array of %BR% \
  <b>HRDATA[31:0]</b> | %BR% \
amba_ahb_ri.s_amba_ahb_al(3 downto 1).HRDATA_vl(31 downto 0)                          | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HRDATA_vl(31 downto 0)                                                 |
| ||||
| <b>HRESETn</b>      | amba_ahb_ri.m_amba_ahb_rl.HRESET_nl                           | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HRESET_nl |
| <b>HCLK</b>         | amba_ahb_ri.m_amba_ahb_rl.HCLK_l                              | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HCLK_l |
| <b>HREADY</b>       | amba_ahb_ri.m_amba_ahb_rl.HREADY_l                            | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HREADY_l |
| <b>HADDR[31:0]</b>  | amba_ahb_ri.m_amba_ahb_rl.HADDR_vl(31 downto 0)               | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | amba_ahb_ri.m_amba_ahb_rl.HWRITE_l                            | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HWRITE_l |
| <b>HSIZE[2:0]</b>   | amba_ahb_ri.m_amba_ahb_rl.HSIZE_vl(2 downto 0)                | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | amba_ahb_ri.m_amba_ahb_rl.HBURST_vl(2 downto 0)               | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | amba_ahb_ri.m_amba_ahb_rl.HPROT_vl(3 downto 0)                | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | amba_ahb_ri.m_amba_ahb_rl.HTRANS_vl(1 downto 0)               | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | amba_ahb_ri.m_amba_ahb_rl.HMASTLOCK_l                         | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | amba_ahb_ri.m_amba_ahb_rl.HWDATA_vl(31 downto 0)              | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HWDATA_vl(31 downto 0) |
| ||||
| <b>HSEL[3:1]</b>    |                                                               | <b>return</b> | amba_ahb_rif.HSEL_vl(3 downto 1) |
| ||||
| *Multiplexor Function:* ||
| ahbl_master_inst.slave_multiplexor_asgn ||
| *Name*              | *Input Element*                                               | *Mode*        | *Composite Signal or Element* |
| array of %BR% \
  <b>HSEL</b>         | %BR% \
amba_ahb_ri.HSEL_vl(3 downto 1)                                                       | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.HSEL_vl(3 downto 1)                                                                              |
| ||||
| array of %BR% \
  <b>HREADYOUT</b>    | %BR% \
amba_ahb_ri.s_amba_ahb_al(3 downto 1).HREADYOUT_l                                     | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HREADYOUT_l                                                            |
| array of %BR% \
  <b>HRESP</b>        | %BR% \
amba_ahb_ri.s_amba_ahb_al(3 downto 1).HRESP_l                                         | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HRESP_l                                                                |
| array of %BR% \
  <b>HRDATA[31:0]</b> | %BR% \
amba_ahb_ri.s_amba_ahb_al(3 downto 1).HRDATA_vl(31 downto 0)                          | %BR% \
<b>in</b>                                                                                             | %BR% \
amba_ahb_rif.s_amba_ahb_al(3 downto 1).HRDATA_vl(31 downto 0)                                                 |
| ||||
| <b>HRESETn</b>      | amba_ahb_ri.m_amba_ahb_rl.HRESET_nl                           | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HRESET_nl |
| <b>HCLK</b>         | amba_ahb_ri.m_amba_ahb_rl.HCLK_l                              | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HCLK_l |
| <b>HREADY</b>       | amba_ahb_ri.m_amba_ahb_rl.HREADY_l                            | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HREADY_l |
| <b>HADDR[31:0]</b>  | amba_ahb_ri.m_amba_ahb_rl.HADDR_vl(31 downto 0)               | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HADDR_vl(31 downto 0) |
| <b>HWRITE</b>       | amba_ahb_ri.m_amba_ahb_rl.HWRITE_l                            | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HWRITE_l |
| <b>HSIZE[2:0]</b>   | amba_ahb_ri.m_amba_ahb_rl.HSIZE_vl(2 downto 0)                | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HSIZE_vl(2 downto 0) |
| <b>HBURST[2:0]</b>  | amba_ahb_ri.m_amba_ahb_rl.HBURST_vl(2 downto 0)               | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HBURST_vl(2 downto 0) |
| <b>HPROT[3:0]</b>   | amba_ahb_ri.m_amba_ahb_rl.HPROT_vl(3 downto 0)                | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HPROT_vl(3 downto 0) |
| <b>HTRANS[1:0]</b>  | amba_ahb_ri.m_amba_ahb_rl.HTRANS_vl(1 downto 0)               | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HTRANS_vl(1 downto 0) |
| <b>HMASTLOCK</b>    | amba_ahb_ri.m_amba_ahb_rl.HMASTLOCK_l                         | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HMASTLOCK_l |
| <b>HWDATA[31:0]</b> | amba_ahb_ri.m_amba_ahb_rl.HWDATA_vl(31 downto 0)              | <b>in</b>     | amba_ahb_rif.m_amba_ahb_rl.HWDATA_vl(31 downto 0) |
| ||||
| <b>HREADYOUT</b>    |                                                               | <b>return</b> | s_amba_ahb_rs.HREADYOUT_l |
| <b>HRESP</b>        |                                                               | <b>return</b> | s_amba_ahb_rs.HRESP_l |
| <b>HRDATA[31:0]</b> |                                                               | <b>return</b> | s_amba_ahb_rs.HRDATA_vl(31 downto 0) |
| ||||

-- %USERSIG{BrentHayhoe - 2016-09-09}%

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Topic revision: r1 - 2016-09-27 - 10:50:21 - TWikiGuest
P1076/Ballots