(r5) PreponedProcess < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>PreponedProcess (revision 5) (raw view)~~EditAttach~~
---+ Preponed Processes

%TOC%

---++ Proposal Editing Information
   * Who Updates: Main.JimLewis, &lt;Add YourName&gt;, ...
   * Date Proposed: 2012-08-19
   * Date Last Updated: 2012-08-19
   * Priority:
   * Complexity:
   * Focus: Testbench
---++ Requirement Summary

Run a process or statement during a special execution cycle or cycles that precede the first regular execution.

---++ Rationale

Intended for clocks and/or initialization of dynamic data structures built in a protected type.

---++ Related and/or Competing Issues: None

---++ Use Model 1: Initializing Data Structures

The following runs once at the start of the time.
<verbatim>InitProc : preponed process
begin
    Mem.InitMemory (AddrBits => 8, DataBits => 16) ; 
    wait ; 
end process InitProc ; </verbatim>

---++ Use Model 2: Clock Gating

The intent is that Clk and Clk2 both change before any non-preponed processes can run,and hence, the non-preponed processes see the change at the same time.
<verbatim>preponed : Clk <= not Clk after 20 ns ; 
preponed : Clk2 <= Clk and ClockGate ;  </verbatim>

---++ Proposal

---++ Questions

---++ General Comments

-- Main.ErnstChristen - 2015-01-27

There are 2 proposals related to clock management.
   * [[P1076.ClockedShorthand][Clocked Shorthand]]
   * [[P1076.PreponedProcess][Preponed Processes (clocks)]] - This proposal

It seems worthwhile to formulate generic requirements for handling clocks (semantics, usage, restrictions, etc.) before looking at individual aspects in isolation.


-- Main.TristanGingold - 2016-06-04 (via Email)

Complexity is very low, this will simply add a new stratum, like postponed.

I am not convinced by use case #1.  Values can be assigned by
a default value; and initialization using procedure is usually
done within reset.

Use case #2 is more interesting.  Propagation through nets is
immediate, contrary to signal assignment.  With vhdl 2008, it
is possible to add logic in port map but they are delayed by
one delta cycle.  As far as I know, it is not easy to do
logic on clocks.  But I think this case must be dug a bit more.

---++ Supporters

-- Main.MortenZilmer - 2015-01-21

-- Main.PatrickLehmann - 2016-08-01
Topic revision: r1 - 2020-02-17 - 15:34:57 - TWikiGuest
P1076/Ballots