2State < P1076/Ballots

P1076/Ballots Web>Vhdl2019CollectedRequirements>2State (2020-02-17, JimLewis) (raw view)EditAttach
---+ Define 2 & 4 State Semantics for std_ulogic

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---++ Recommendation: Investigate Further

---++ Proposal Information
   * Who Updates:
   * Date Last Updated
   * Priority:
   * Complexity:
   * Focus: Performance

---++ Requirement Summary & Rationale

[[http://www.eda.org/vhdl-200x/vhdl-200x-perf/proposals/perf03.txt"][Proposal here]]

---++ Arguments For

_Add your signature here to indicate your support for the proposal_

---++ Arguments Against

_Add your signature here to indicate your do not support for the proposal_

[[2013_MeetingJanuary31][From Jan 31, 2013 meeting]]
   * 
      * Simulate std_logic using 2 states (0, 1) or 4 states (0,1,X,Z)
      * Could this buy us anything?
      * Where would it be specified to do this? Is it a tool thing?
      * Does bit simulate faster / use less memory that std_logic?
      * Why can't a compiler/simulator do this automatically for RTL code? 
         * If I cannot do it, can I mark it somehow?
         * Simulator flag or marker in code?
      * Recommendation: Investigate Further

---++ General Comments

-- Main.ErnstChristen - 2015-01-27 - Such semantics are already available: STD.STANDARD.BIT and IEEE.STD_LOGIC_1164.X01Z and the related conversion functions.
---+++ Email Reflector Comments

   * [[http://www.eda.org/vhdl-200x/vhdl-200x-perf/hm/][Original VHDL-200X Simulation Performance Reflector Archive]]

---++++ From: [[Main.PeterFlake][Peter Flake]] (Thu Jan 03 2013 - 09:48:21 PST)

Perf 3: Define 2 and 4 state semantics

Since the language allows 2 state and 4 state signals to be defined, it seems unnecessary to change the language. Of course a tool can attempt to optimise std_logic into fewer states, at the risk of getting the wrong results!

---++++ From: [[Main.JoanneDegroat][Joanne Degroat]] (Thu Jan 03 2013 - 11:38:20 PST)

On Perf 3: Define 2 and 4 state semantics

The language allows for development of any state systems needed for the task at hand through overloading. I recently had the need to develop a logic system with probabilistic fault injection, i.e., a logic function randomly generates the wrong result. This can be done. If the logic system developed has merit it can be incorporated as a package in the standard.

---++++ From: [[Main.BrentHahoe][Brent Hayhoe]] (Mon Jan 21 2013 - 13:09:26 PST)

PERF-03 Define 2 & 4 state semantics

As has already been said, the types required already exist. I think the answer is/are types 'BIT' and 'X01Z', just needs a resolution function for 'BIT'.
Topic revision: r4 - 2020-02-17 - 15:34:49 - JimLewis
P1076/Ballots