(r4) 2016_MeetingSeptember7 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2016_MeetingSeptember7 (revision 4) (raw view)~~EditAttach~~
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---+!! P1076 Wednesday September 7, 2016 Meeting Minutes

---++!! Attendees:
   * Patrick Lehmann, Peter Flake, Kevin Jennings, Jim Lewis

---++!! Agenda:

%TOC%

---++ Meeting Discussion
   * Need to vote on P&P
      * AI: Jim send link to WG
   * Interfaces - continue & Brent's example
      * Peter Proposed simplified view that combines record with the port that may have applications under some/many main stream test cases.
   * Looking at collected requirements list for unbinned items.
      * [[ComposingExteranlPathName]] - Some day maybe
      * [[ExtendedStringLiterals]] - C like strings -
         * No big change for the compiler
         * Low priority enhancement
      * [[TimingConstraints]] -
         * Jim: Something for a synthesis working group
         * Consensus: not for 1076
      * [[ExtendedIntegers]] - move to integer category
      * [[AttributeShorthand]] - some day maybe
      * [[SupportReal]] - ?tool thing? - ?synthesis?
         * If we were to provide a mechanism that made the size of the exponent and mantissa specifiable during synthesis, if it exceeded the size currently implemented by type real, how would it actually be simulated during an RTL simulation?
         * Would require a corresponding language update to support extended ranges on type real.
         * Categorize under synthesis
         * some day maybe
      * [[SynthesizableEvent]] - proper coding styles for ddr ff already implemented by 1076.6. Reject
      * [[PhysicalTypeRange]] - integer and/or enhancement
      * [[ExtendedRanges]] - enhancement
      * [[ExtendedUserDefinedAttributes]] - purpose attach function to an attribute
         * Attribute would be an alias to an existing function.
         * complexity?
         * Where and how use? Extended ranges -
         * Perhaps apply attribute to type in a package. example: to_string attribute for composites
         * ?enhancement / some day attribute?
         * When would corresponding function get called?
         * Needs use case to demonstrate value
         * enhancement conditionally accepted with Patrick required to get relevant motivating example otherwise downgrade to some day maybe
         * mechanism to map composite type to string?
      * [[EnhancedIntegers]]
         * binned with integer proposals
      * [[ObjectInspection]]
         * Can't we already do: signal_name'simple_name and signal_name'subtype'simple_name
         * Could this be related to any of the introspection proposals?
         * reject: wg requires improved use case.
      * [[GraphicsLibrary]]
         * forward to open source package / library wg
         * implement as an application of DPI
      * [[RegularExpressions]]
         * What sort of regular expressions and what do you plan to do with them?
         * package vs DPI vs PSL??
         * Need use model and more details?
         * forward to open source group for initial implementation and/or resolution of use model?
<verbatim>type spi_master_r is record
 mosi : std_logic; -- Data from master to slave
 miso : std_logic; -- Data from slave to master
 sclk : std_logic; -- Serial clock
 ssel : std_logic_vector -- Chip selects (active-low)
 end record spi_master_r;
port view master of spi_master_r is
 mosi => out;
 miso => in;
 sclk => out;
 ssel => out;
 end port view master;
could be combined using port syntax:
type spi_master_r is port record
 mosi : out std_logic; -- Data from master to slave
 miso : in std_logic; -- Data from slave to master
 sclk : out std_logic; -- Serial clock
 ssel : out std_logic_vector -- Chip selects (active-low)
end port record
'record to extract record declaration
'reverse/... to reverse
'in for input only - ie: monitor
port view master2 of spi_master_r'record is
-- ...
end port view;

attribute to_string : string;
attribute to_string of std_logic : type is myFunc(10);
attribute to_string of std_logic : type is myFunc[std_logic return string];
alias foo is myFunc[integer return string];

signal clock : std_logic;
process
begin
 report myfunc(clock);
report std_logic'to_string(clock);
 
end process;</verbatim>
---++ Review and Approve Meeting Minutes and Decisions by Attendees

Patrick, Peter, Kevin, Jim
---++ Review and Approve Meeting Minutes and Decisions by non-attendees

<Add your name below. Indicate if you agree or disagree>

<If you disagree, add a list of items you disagree with and initiate a reflector discussion>

-- Main.RobGaddi - 2016-09-15 Agree

-- [[Main.BrentHayhoe][Brent Hahoe]]- 2016-09-15 Agree

---++ Next Meeting: Thursday [[2016_MeetingSeptember15][September 15, 2016]], 11 am Pacific
---+++ Previous Meeting: Thursday [[2016_MeetingSeptember1][September 1, 2016]]
Topic revision: r1 - 2020-02-17 - 15:36:18 - TWikiGuest
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