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<!-- * Set ALLOWTOPICCHANGE = P1076AdminGroup --> ---+ P1076 October 10, 2013 Meeting Minutes ---++ Attendees: * Main.RyanHinton * Main.CliffordWalinsky * Main.PeterFlake * Main.JimLewis ---++ Agenda: * Review [[IssueScreening][ISAC issues and Bugzilla]] * Check closure on AI from review lists. * Review items in the [[http://www.eda.org/twiki/bin/view.cgi/P1076/Vhdl2019CollectedRequirements][collected requirements list]] ---++ Old ISAC IR Review * Review Cliff W findings on * Are port clauses ordered (like generics)? <verbatim> data_real : in sfixed; data_imag : in data_real'subtype; </verbatim> Paragraph 6.5.6.1 allows ordering for generic lists, but not port and parameter lists. Will require a language change. Cliff indicated that it is not a huge impact on compilers. * * IR 2063 - FT Item 14 - Looks like was addressed. * IR 2054 & 2063 keep open. * IR 2110 - Done. Implicit type coversions * IR 2112 - Done. In VHDL-2008 entity and architecture declarative regions were merged. * Ryan AI * 2065 - Ryan added proposal [[RelaxedOthersAggregate]] ---++ New ISAC IR Review * 2132 * First blush: seems similar to having an attribute on an out parameter * Much more complex though. Multiple operator expressions, and functions that call functions * Ryan and Jim do not think this is a good idea * To go forward needs champion * Needs tracking proposal - AI Ryan * 2130 - Overload ":=" Operator * Causes OMG by the compiler people * To go forward needs champion * Needs tracking proposal - AI Jim * 2131 - VHPI updates * Did 2008 fix this? Is this a necessary change? * AI Peter to look at it. ---++ Review and Approve Meeting Minutes: * Motion: Cliff 2nd: Peter ---++ Next Meeting Date (proposed): Thursday [[2013_MeetingOct24][Oct 24, 2013]], 8 am Pacific Previous Meeting: [[2013_MeetingSept26][Sept 26, 2013]]
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