======================================================================== Draft of White Paper on VHDL-AMS Subset for REAL-TIME Eduard Moser, Robert Bosch GmbH, moser@fli.sh.bosch.de ======================================================================== 0 Introduction The following syntax and additional comments describe the VHDL-AMS (IEEE 1076.1) language subset for REAL-TIME (in short VHDL-AMS-RT). VHDL-AMS is the first international accepted standard for mixed analog and discrete systems. It is suitable to support many application domains for behavioural modelling, particularly for mixed-domain systems the language is of major interest. For control engineering and (physical) plant design real-time simulation is an efficient means to interact with the "real" components either the controller or the plant. Real-time simulation supports the design and verification of control algorithms and the design of plants, this includes parameter extraction and adjustment since the modelling of physical systems is only close but never exact. The VHDL-AMS-RT can only include language concepts which would do not contradict the following precondition: ---------------------------------------------------------------------- The required calculation time for each time step must stay below some predictable maximum time. ---------------------------------------------------------------------- This constraint requires an evaluation of each time step with no or previously determined (constant bounded) number of iterations. It excludes algebraic constraints and non predictable process interaction. Since the simulation speed alone decides if and only if an application can be supported at real-time, additional restrictions for fast and efficient simulation constrain the subset further. Time consuming concepts are not supported. The VHDL-AMS-RT is based on the [2] and the section numbering corresponds to this document. This document is a result of the EC funded projects TOOLSYS (Brite-Euram Project BE3249, BRPR-CT96-0303) and ODECOMS (Brite-Euram Project BPRP-CT97-567). 0.1 General Approach The basic concept is Block Diagram modelling according to [1, 136ff]. Each component can be described as a block whose behaviour can be expressed by the following equations: x'dot = f(x, u, t) y = g(x, u, t) (with input vector u, output vector y, state vector x, and time t). The functions f and g may be non-linear and discontinuous. The input/output waveforms are continuously defined (QUANTITY). This definition still allows algebraic constraints if and only if there exists a algebraic loop of n blocks such that z_i = h_i(..., z_i-1, ...) z_1 = h_1(..., z_n, ...) (with h_i() being the "functions" related to some block i and z_i being some continuous waveforms connecting the blocks) But this can be determined by tools and these models will be rejected. 0.2 Procedural Code: Subprograms, Expressions, etc. Most semantic constructs of the language have corresponding constructs in regular procedural programming languages (e.g. C). This includes the subprograms (procedures and functions) and most of the sequential code. (Code with no reference to time.) This code is entirely supported. Within subprograms wait statements, signal assignment statements and most attributes are not supported (supported attributes within subprograms see #14.1.3). 0.3 Libraries and Packages supported. 0.4 Discrete VHDL The VHDL-AMS-RT of the discrete VHDL is derived from [3] with additional constraints and one additional feature. This pragmatic approach was chosen, since it fits most of our needs. The discrete descriptions written according to the draft standard will be reusable for synthesis and therefore, the concepts are most likely easy and fast to simulate. There are some minor additional constraints (e.g., no resolution functions [#4.2]). All the other REAL-TIME specific restrictions are described in the following subsections. The purely syntactical constraints regarding the optional extension of the keyword END with the corresponding keywords (e.g., ENTITY) were relaxed for VHDL-AMS-RT in order to keep the language more consistent. 0.5 Sequential Statements (#8) Supported but no assertion statement, report statement [#8.2] are allowed. One additional feature is added to the subset definition [3], this feature concerns the wait statement. Assertions (including the reporting mechanism) are very well suited for monitoring the models during simulations, but the additional time and the required input/output mechanism does not seem appropriate for real-time applications. The signal assignment statement does not support the delay mechanism [#8.4]. The delay mechanism has to be substituted by explicitely using wait statements (this substitution is not equivalent). In [3] the wait statement is restricted to only one statement within each process. For the modelling within hydraulics and mechanics, it is convenient to relax this restriction. (E.g., for modelling stick/slip friction, one has to describe a finite state machine with two states. This can easily be done using one process with two wait statements.) The sequential break statement is discussed later. 0.6 Concurrent Statements (#9) Supported the restrictions as for sequential statements (see above). The block statement and the postponed and guard feature are not supported. ?? Since the generate statement is of little use for the mentioned application domains, it should be rejected. 0.7 Discrete Communication: Signals Signals are the basic unit for communication between processes. They allow to communicate events including attached information. Signals have to be supported. The restrictions are according to [3]. The restrictions are mainly defined within the predefined environment [#14.1] and do not allow using history information of the signal. This makes the handling of signals much easier. For the reasons explained below (section 0.13) no communication via signals is supported between components. Therefore, the PORT SIGNAL is not supported. 0.8 Analog and Mixed-Signal VHDL The analog and mixed-signal part, meaning the additional features which are introduced by VHDL-AMS, describe the necessary features for modelling hydraulics, mechanics and electronics. Only very few concepts can be deleted. 0.9 Quantities Quantities are continuous wave-forms whose behaviour is determined by simultaneous statements [#15] (some of the quantities are state variables). Their use is restricted according to section 0.10. This document calls some quantities ``to-be-determined-quantities'', these quantities are either free quantities or interface quantities of mode out (PORT (QUANTITY q: OUT real)). 0.10 Simultaneous Statements The subset defines the restriction stated in Section 0.1 to support only systems which can be coded according to Block Diagrams as restrictions on the shape of the equations but these have no impact on the expressive power. These restrictions are introduced to achieve better error messages and facilitate code generation. All simultaneous statements are based on simple simultaneous statements - equations. These simple simultaneous statements are restricted to one of the following forms: Assigned Equations (ASE): q_i = f_i(..., q_k, ...) Ordinary Differential Equations (ODE): q_j'dot = g_j(..., q_k, ...) Each to-be-determined-quantity q_i is exactly on the left-hand-side of one equation of either ASE or ODE. f_i and g_j can depend on quantities, signals and time (function now), but f_i has to be independent of q_i . The functions on the right hand side are ``expressions'' in VHDL-AMS terminology, and represent anything which could be written as a function of the above mentioned arguments (e.g., f(force, vel, c) = force - sign(vel) * c). Furthermore, the derivative (attribute) ( q = q'dot) can only appear as left-hand-side of ODE. The derivative are not allowed as argument on the right-hand-side in any equation, the integral (attribute q'integ) is not allowed at all. The model is within the VHDL-AMS-RT only if the set of ASE has the following properties: 1. Each equation in the set q_i = f_i() is indexed as eq_i. 2. If q_i appears in eq_j follows eq_i < eq_j . 3. < is a partial order. (These properties guarantee that all of these equations can be evaluated as a sequence of assignment statements, no iteration is necessary.) All simultaneous statements are compositions of simple simultaneous statements. For simultaneous if and case statements, the number of simultaneous statements for each branch has to be the same. Only the same equation types and same quantities on the left-hand-side are allowed for each branch of simultaneous_if and case_statement. 0.11 Analog Communication Only one communication mechanism is supported: The communication is handled using interface quantities (PORT QUANTITY) which carry always their respective information direction. Remark: Energy conserving communication is not supported within the VHDL-AMS-RT, since its simulation needs the resolution of algebraic equations and can not always be resolved without bounded numerical iteration. Without energy conserving communication neither terminals nor natures have to be supported. 0.12 Analog - Discrete Interaction The break statement [#8.14, #9] and the predefined attribute q'above(expression) [#14.1] are supported. 0.13 Simulation Cycle - Maximum Number of Delta Cycles The maximum number of delta cycles should be predictable for each architecture. To be discussed: Some relaxation might be necessary since delta cycles due to analog interaction are probably not predictable. 0.14 Time The simulation cycle has to be treaded as defined in [2]. Only the notion of time (having a continuous as well as a discrete time) has to be analysed in respect to the real-time needs. The real-time simulation will be based on fixed cycle time simulation. 0.15 Objects Within the subset file declaration, group template declaration, group declaration, nature declaration, subnature declaration and terminal declaration are not supported. 1 Design entities and configurations 1.1 Entity declarations as defined in [2]. 1.2 Architecture bodies supported, (objects only according to section 0.15). 1.3 Configuration declaration To be discussed: The document [3] is very restrictive on configuration. It might be relaxed. 2 Subprograms and Packages As discussed above, signal assignment and wait statement are not supported within subprograms. Furthermore, only some attributes on signals and quantities are supported. 3 Types and Natures 3.6 Natures Natures are not supported within VHDL-AMS-RT. 4 Declarations Only objects according to section 0.15 can be declared. 5 Specification as defined but no entity aspect, guarded signal specification and disconnect specification. 6 Names as defined in [2]. 7 Expressions as defined but no allocator. 8 Sequential Statements Most sequential statements have equivalent versions in other procedural languages. Only the wait statement and the break statement necessary additional concepts. The assertion statement and the report statement can be ignored. 8.1 Wait Statement The wait statement is not allowed in subprograms (only allowed in processes). 8.2 Assertion Statement The assertion statement is not supported. 8.3 Report Statement The report statement is not supported. 8.4 Signal Assignment Statement The signal assignment statement is not allowed in subprograms (only allowed in processes). Only one waveform without delay is supported. 8.5 Variable Assignment Statement supported. 8.6 Procedure Call Statement supported. 8.7 If Statement supported. 8.8 Case Statement supported. 8.9 Loop Statement supported. 8.10 Next Statement supported. 8.11 Exit Statement supported. 8.12 Return Statement supported. 8.13 Null Statement supported. 8.14 Break Statement 9 Concurrent Statements The document [3] does not allow more than one wait statement within one process. This VHDL-AMS-RT skips this constraint. The features GUARD and POSTPONED are not supported. 9.1 Block statement not supported. 9.2 Process statement supported. 9.3 Concurrent procedure call statement supported. 9.4 Concurrent assertion statement not supported (see 0.5). 9.5 Concurrent signal assignment statement With one waveform without without delay is supported. 9.6 Component instantiation statement supported. 9.7 Generate statement ?? supported. (Not a necessary feature for the application domain, might be rejected.) 9.8 Concurrent break statement supported. 10 Scope and Visibility as defined in [2]. 11 Design Units and Their Analysis as defined in [2]. 12 Elaboration and Execution as defined in [2]. 13 Lexical Elements as defined in [2]. 13.1 Reserved Words as defined in [2]. 14 Predefined Language Environment The set of predefined attributes is reduced to a manageable amount.
14.1.1 Predefined attributes supported outside subprograms
14.1.2 Desirable predefined attributes supported outside subprograms
14.1.3 Predefined attributes supported within subprograms
14.2 Package STANDARD supported. Severity level ignored. 14.3 Package TEXTIO 15 Simultaneous Statements As defined in section 0.10. --------------------------------------------------------------------------- References [1] D'Azzo and Houpis. Feedback Control for Analysis and Synthesis. John Wiley & Sons, 1967. [2] IEEE, New York. IEEE Standard VHDL Language Referenz Manual (Integrated with VHDL-AMS changes), Draft, 1997. [3] IEEE, New York. IEEE P1076.6/D1.12 Draft Standard For VHDL Register Transfer Level Synthesis, 1998. [4] Extended White Paper on VHDL-AMS Subset for Real-Time (in preparation).