Peter, Thank you. The full P1076-2007/D3.4 draft LRM is still under restricted, non public, access in Accellera web site. I can however get a copy for people in the WG who will review the changes, namely those who contributed to the 1076.1 LRM. Best regards, Alain Peter Ashenden wrote: > Alain, > > Annex D of the draft contains a list of changed sections. I've extracted > those pages from P1076-2007/D3.4 for your information. > > Beyond that, Jim Lewis and I are preparing a book for publication describing > the new features. If should be published around October this year. > > Hope this helps. > > Cheers, > > PA > > -- > Dr. Peter J. Ashenden peter@ashenden.com.au > Ashenden Designs Pty. Ltd. www.ashenden.com.au > PO Box 640 VoIP: sip://0871270078@sip.internode.on.net > Stirling, SA 5152 Phone: +61 8 7127 0078 > Australia Mobile: +61 414 70 9106 > > >> -----Original Message----- >> From: Alain Vachoux [mailto:alain.vachoux@epfl.ch] >> Sent: Wednesday, 16 May 2007 18:14 PM >> To: Peter Ashenden >> Cc: '1076.1 mailing list' >> Subject: Re: [1076.1] Proposals for new features open for discussion >> >> >> Peter, >> >> Is it possible to get the complete list of changes to VHDL without >> having to browse through the P1076-2007 LRM to find them out? >> >> Thanks and regards, >> Alain >> >> Peter Ashenden wrote: >>> Alain, >>> >>> It might be worth having the VHDL-AMS WG review the changes >> to VHDL in >>> P1076-2007 to see how they affect the AMS features. Many of the >>> changes are independent of AMS, but others are not. For example, >>> changes to the way constraints apply to composite types >> should also be >>> mirrored in composite natures. It would be worth finding out any >>> issues early, so that they can be addressed in good time for a >>> revision of 1076.1. >>> >>> Cheers, >>> >>> PA >>> >>> -- >>> Dr. Peter J. Ashenden peter@ashenden.com.au >>> Ashenden Designs Pty. Ltd. www.ashenden.com.au >>> PO Box 640 VoIP: >> sip://0871270078@sip.internode.on.net >>> Stirling, SA 5152 Phone: +61 8 7127 0078 >>> Australia Mobile: +61 414 70 9106 >>> >>> >>>> -----Original Message----- >>>> From: owner-vhdl-ams@server.eda.org >>>> [mailto:owner-vhdl-ams@server.eda.org] On Behalf Of Alain Vachoux >>>> Sent: Wednesday, 16 May 2007 1:59 AM >>>> To: Muranyi, Arpad >>>> Cc: 1076.1 mailing list >>>> Subject: Re: [1076.1] Proposals for new features open for >> discussion >>>> >>>> Arpad, >>>> >>>> It is true that the 1076.1-2007 standard is based on >> 1076-2002 which >>>> does not support encryption capabilities. We'll need another IEEE >>>> ballot to formally have 1076.1 based on 1076-2007 (and to formally >>>> include the >>>> encryption mechanism in VHDL-AMS), which may not happen very >>>> soon. This >>>> is because there are two reasons to proceed to an IEEE >>>> ballot, whichever >>>> comes first: >>>> 1) To have significant changes or additions to bring to the >>>> standard, or >>>> 2) To reach the 5-year deadline for reaffirmation. >>>> Meanwhile, I expect that 1076-2007 will be released and that >>>> tools will >>>> support it more or less rapidly, so VHDL-AMS users will also >>>> be able to >>>> use encryption facilities. I'm of course assuming that the >> 1076-2007 >>>> spec is appropriate for 1076.1 as it is. >>>> >>>> Best regards, >>>> Alain >>>> >>>> Muranyi, Arpad wrote: >>>>> Alain, >>>>> >>>>> I wonder whether this is the right approach. I mean to >> wait for the >>>>> tool vendors to implement it first and then put it in the spec. >>>>> Shouldn't it be the other way around? >>>>> >>>>> Arpad =========================================================== >>>>> >>>>> -----Original Message----- >>>>> From: Alain Vachoux [mailto:alain.vachoux@epfl.ch] >>>>> Sent: Tuesday, May 15, 2007 8:43 AM >>>>> To: Mirmak, Michael >>>>> Cc: olivier.rolland@systemsvip.com; Muranyi, Arpad; 1076.1 >>>> mailing list >>>>> Subject: Re: [1076.1] Proposals for new features open for >> discussion >>>>> Michael, >>>>> >>>>> As I replied to Arpad, VHDL 1076.1 will naturally endorse the VHDL >>>>> 1076-2007 encryption scheme. As far as we can see, there is >>>> nothing in >>>>> VHDL-AMS that would hinder the use of the protection >> mechanism. Now >>>>> it is a question of time until EDA tools are upgraded >>>> to support the >>>>> new encryption capabilities. >>>>> >>>>> Best regards, >>>>> Alain >>>>> >>>>> Mirmak, Michael wrote: >>>>>> All, >>>>>> >>>>>> Per Arpad's note, we are interested in seeing the >> encryption macro >>>>>> language, currently in both the Accellera 1076 VHDL >>>> updated draft and >>>>>> the IEEE 1364 Verilog specification Annex H, "migrate >>>> down" into the AMS >>>>>> specifications. IC vendors are concerned about IP >>>> protection, and the >>>>>> macro approach seems to be the most general-purpose way of >>>> accommodating >>>>>> IP protection while taking tool variations and national >>>> policies into >>>>>> account. As IBIS now supports links to both AMS >>>> languages, IC vendors >>>>>> interested in distributing IBIS+AMS models for signal integrity >>>>>> simulations are becoming concerned. >>>>>> >>>>>> The encryption-versus-scrambling debate has been fought on this >>>>>> reflector and others like it before. As it tends to >>>> generate more heat >>>>>> than light, I would like to avoid it entirely. Can the macro >>>>>> approach be expanded to support both? >>>>>> >>>>>> - Michael Mirmak >>>>>> Intel Corp. >>>>>> Chair, EIA IBIS Open Forum >>>>>> http://www.eigroup.org/ibis/ >>>>>> http://www.eda-twiki.org/ibis/ >>>>>> >>>>>> >> --------------------------------------------------------------------- >>>>>> --- >>>>>> *From:* owner-vhdl-ams@server.eda.org >>>>>> [mailto:owner-vhdl-ams@server.eda.org] *On Behalf Of >>>> *Olivier Rolland >>>>>> *Sent:* Monday, May 14, 2007 12:15 PM >>>>>> *To:* Muranyi, Arpad; 1076.1 mailing list >>>>>> *Subject:* Re: [1076.1] Proposals for new features open >>>> for discussion >>>>>> 1) Make a standard encryption available in VHDL-AMS. >>>>>> >>>>>> I'm not sure about the added value of a standard >> encryption scheme, >>>>>> since there is no real security behind it due to legal >>>> limitations (root >>>>>> key delivery to each country legal authorities and >>>> mandatory decryption >>>>>> of the model for compilation purpose which makes a memory >>>> dump efficient >>>>>> to hach the original VHDL-AMS code) and there is a >>>> solution based over >>>>>> scrambling avalaible which make VHDL-AMS encryption useless. >>>>>> Regards. Olivier Rolland >>>>>> >>>>>> Systems'ViP >>>>>> (Boost your R&D efficiency, implement the functional >>>> Virtual Prototyping >>>>>> with us) <http://www.systemsvip.com> >>>>>> >>>>>> >>>>>> *Dr. Olivier Rolland* >>>>>> /CEO >>>>>> / 4 Rue Boussingault >>>>>> F - 67000 Strasbourg >>>>>> <http://www.systemsvip.com> >>>>>> olivier.rolland@systemsvip.com >>>> <mailto:olivier.rolland@systemsvip.com> >>>>>> www.systemsvip.com <http://www.systemsvip.com> >>>>>> tel: +33 671 128 130 >>>>>> fax: +33 874 761 346 >>>>>> mobile: +33 671 128 130 >>>>>> >>>>>> >>>>>> >>>>>> This e-mail, including attachments, is intended for the >>>> person(s) or >>>>>> company named and may contain confidential and/or legally >>>> privileged >>>>>> information. Unauthorized disclosure, copying or use of >>>> this information >>>>>> may be unlawful and is prohibited. If you are not the intended >>>>>> recipient,please delete this message and notify the sender >>>>>> >>>>>> >>>>>> >>>>>> Muranyi, Arpad a écrit : >>>>>>> Alain, >>>>>>> >>>>>>> I wonder whether it was possible to add two topics to the list: >>>>>>> >>>>>>> 1) Make a standard encryption available in VHDL-AMS. >>>>>>> 2) S-parameter support in the VHDL-AMS language through >>>>>>> some functions similar to "lpf". >>>>>>> >>>>>>> Thanks, >>>>>>> >>>>>>> Arpad >>>>>>> =============================================================== >>>>>>> >>>>>>> >>>>>>>> -----Original Message----- >>>>>>>> From: owner-vhdl-ams@server.eda.org >>>>>>>> [mailto:owner-vhdl-ams@server.eda.org] On Behalf Of >> Alain Vachoux >>>>>>>> Sent: Tuesday, May 01, 2007 2:19 AM >>>>>>>> To: 1076.1 mailing list >>>>>>>> Subject: [1076.1] Proposals for new features open for dicussion >>>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> As mentioned in the minutes of the last working group >> meeting, a >>>>>>>> new page has been created on the P1076.1 web site at >>>>>>>> http://www.eda-stds.org/vhdl-ams/wwwpages_new/new_features.html >>>>>>>> which contains first drafts of proposals for new >> features in the >>>>>>>> VHDL-AMS language or new standard packages. >>>>>>>> >>>>>>>> The page includes the definition of the process we'll >> follow and >>>>>>>> the definition of the form of proposals. It also currently >>>> lists three >>>>>>>> proposals in various degrees of achievement: >>>>>>>> - Mixed Netlists >>>>>>>> - Table Data Types and Lookup Functions >>>>>>>> - Requirements and Verification >>>>>>>> >>>>>>>> I highly encourage you to study these proposals, make >>>> comments and >>>>>>>> contribute to the proposals. The discussion can be done >>>> in the 1076.1 >>>>>>>> mailing list vhdl-ams@vhdl.org and in the next working >>>> group meetings. >>>>>>>> Currently there is no deadline on when the discussion >>>> should stop and >>>>>>>> decisions have to be made in the working group. >>>>>>>> >>>>>>>> If you have other suggestions for new features, please consider >>>>>>>> submitting me a document which is close to the form that >>>> is defined in >>>>>>>> the web page. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Alain Vachoux >>>>>>>> >>>>>>> >>>>>> -- >>>>>> This message has been scanned for viruses and >>>>>> dangerous content by *MailScanner* >>>> <http://www.mailscanner.info/>*, and is >>>>>> believed to be clean. >>>>>> -- >>>>>> This message has been scanned for viruses and >>>>>> dangerous content by *MailScanner* >>>> <http://www.mailscanner.info/>, and is >>>>>> believed to be clean. * >>>> -- >>>> This message has been scanned for viruses and >>>> dangerous content by MailScanner, and is >>>> believed to be clean. >>>> >>> >>> -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed May 16 04:19:03 2007
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