RE: VHDL-AMS PLI and a Question about the Simulation Cycle

Thanks for taking the time to respond Ernst.

Perhaps my question was not properly framed. I do understand that once
determined, the analog solution point for a cycle need not be
re-determined unless required and also that the analog solver solves at
the start of every cycle with no direct dependence on digital events. 

I am trying to determine if a particular synchronization strategy is
specified by the language for the analog and digital simulators (by
allowing the analog solver to only advance at most by the next digital
event time). 

A simple mixed signal example - a 2 bit counter with the most
significant bit affecting an analog system which has a time varying
solution. Per the LRM, won't the analog solver be executed even when the
least significant bit changes? 

Thanks,
Sameer



-----Original Message-----
From: Ernst Christen [mailto:Ernst.Christen@synopsys.COM] 
Sent: Thursday, January 04, 2007 3:55 PM
To: Sameer Kher
Cc: vhdl-ams@vhdl.org
Subject: RE: VHDL-AMS PLI and a Question about the Simulation Cycle

Sameer,

Your statement about the analog solver executing at every digital event
is not correct.  
The execution of the analog solver is related to cycles, not events.
There are cycles with more than one event, and there are cycles with no
event at all.

Regarding the second part of your question, I direct you again to
section 12.6.6 of the LRM, which defines what the execution of the
analog solver involves. You should be able to draw the right conclusion
from this section or point to an ambiguity in the definition that
prevents you from reaching a conclusion.

Ernst Christen

On Thu, 4 Jan 2007 14:51:29 -0500, Sameer Kher wrote:
> Thanks Ernst,
>
> So I am correct in my interpretation of the simulation cycle that the 
> analog solver must be executed at every digital event (perhaps 
> excluding some delta cycles) irrespective of whether the digital event

> affects the analog system or not?
>
> Thanks John and Martin for the information about the VHPI.
>
> Sameer
>
> -----Original Message-----
> From: Ernst Christen [mailto:Ernst.Christen@synopsys.COM]
> Sent: Thursday, January 04, 2007 2:02 PM
> To: Sameer Kher; vhdl-ams@vhdl.org
> Subject: Re: VHDL-AMS PLI and a Question about the Simulation Cycle
>
> Sameer,
>
> Step a) defines that "The analog solver is executed." Therefore, the 
> analog solver executes at the beginning of each simulation cycle. 
> Clause
> 12.6.6 then defines the actions that the analog solver takes when it 
> executes. These actions depend on the result of step
> g) and other steps, more specifically whether the break flag is set 
> and, to some extent, whether this is a delta cycle or not.
>
> Ernst Christen
>
> On Thu, 4 Jan 2007 10:23:07 -0500, Sameer Kher wrote:
>> Also, I was seeking a clarification on the simulation cycle as 
>> described in the LRM. My question is related to step (g) where the 
>> next simulation time is determined. The text says that the next 
>> simulation cycle "...is determined by setting it to the earliest of :
>> - The value of type universal_time corresponding to TIME'HIGH
>> - The next time at which a driver becomes active, or
>> - The next time at which a process resumes..."
>> Does this imply that the analog solver must execute at every digital 
>> event?
>>
>> Thanks,
>> Sameer Kher
>> R&D Engineer
>> Ansoft Corp.


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