Fair enough and thank you, Arpad!
John, A little correction, if you don't mind... The IBIS folks are not ONLY interested in VHDL-AMS encryption, we are interested in encryption for VHDL-AMS as well as Verilog-A and Verilog-AMS, and probably even Berkeley SPICE and should I dare to say perhaps even legacy IBIS itself. Anyway, it is not just VHDL-AMS we would like to protect. Thanks, Arpad ================================================================== -----Original Message----- From: owner-vhdl-ams@server.eda-stds.org [mailto:owner-vhdl-ams@server.eda-stds.org] On Behalf Of John Shields Sent: Tuesday, June 20, 2006 9:17 AM To: Alain Vachoux Cc: 1076.1 mailing list; Lance Thomson Subject: Re: [1076.1] Information on proposed IP support in VHDL-200X Alain, A bit of a clarification. IMHO, the more appropriate group to engage in discussion is the Accellera VHDL TC. Visit www.accellera.org to add yourself if your company is a member. Lance Thompson, the chair, may know to what extent you might participate even if you are not a member. The vhdl-200x group is not active as their work has transitioned and broadened at the Accellera VHDL TC. He is cc'ed on this email. It is true that many of the same people are on both email reflectors and within the boundaries of the IEEE, it is easy to subscribe/engage working groups. Nevertheless, the work is taking place in Accellera. Their results will move back systematically to the IEEE for review and ballot preparation. A second item that may be of interest if you are attending DAC is that I will be making a presentation on IP encryption at the IBIS Summit meeting sometime on Tuesday morning. They are interested specifically in VHDL-AMS IP, though the focus of the talk will be to provide a general understanding of the mechanism and how it works for any Verilog or VHDL-based HDL. I will at least motivate where issues specific to a particular HDL would lie. Regards, John Shields Alain Vachoux wrote:Dear 1076.1 Working Group member, A couple of months ago, there was some discussion about the support of encryption/decryption for VHDL-AMS models. Ernst Christen mentioned the ongoing effort in the VHDL-200X working group (http://www.eda-stds.org/vhdl-200x/). Since then, I discussed with Lance Thomson, Chair of the Accellera Technical Committee in charge of developing the new VHDL LRM to be submitted to IEEE for revision. We agreed to provide the 1076.1 WG members with documents for information and review. Three documents on IP protection may be then downloaded at the following URLs: http://www.accellera.org/apps/group_public/download.php/532/VHDL_IP_Proposal_V9.doc The original proposal put forward by the VHDL TC extensions committee. It is derived from a donation from Cadence which was derived from their donation to Verilog. http://www.accellera.org/apps/group_public/download.php/634/IP-requirements.pdf A reworked document fixing the low security level provided by some of the use models. This is the base for the new 1076-2006 LRM. http://www.accellera.org/apps/group_public/download.php/682/LCS-2006-140.pdf Actual LRM text that has been added to VHDL (P1076-2006-D2.11) which is currently under review. If you have questions or comments about the proposed IP support, I would suggest to carry the discussion to *both* the 1076.1 and the VHDL-200X mailing list (go to the VHDL-200X web site to subscribe). The IP protection proposal that is being developed is pretty general and should be applicable to 1076.1 models as well. A more detailed review might however reveal some issues specifically related to AMS models. But so far the ownership of the proposal belongs to the VHDL-200X Working Group. Best regards, Alain Vachoux
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