Subject: aliasing natures in VHDL-AMS
From: Ernst Christen (Ernst_Christen@avanticorp.com)
Date: Mon Nov 12 2001 - 18:45:41 PST
Jim,
Thank you for your inquiry. Your assumption that we intended to allow
aliases of natures is correct. Here is the reason that I believe the
LRM definition of aliases is sufficient as it stands.
a) Aliases of natures
Alias declarations are described in section 4.3.3. This section is
quite general and covers the syntax of an alias declaration and the
semantics common to both kinds, object aliases and nonobject
aliases. As you suggest, an alias of a nature a non-object alias.
Section 4.3.3.2 provide rules for non-object aliases *in addition
to* the rules of section 4.3.3. Of these additional rules,
4.3.3.2.a) applies to all nonobject aliases, including aliases of
a nature. All the other rules are specific to certain situations.
There are no other special rules for aliases of a nature, just like
there are no special rules for aliases of a group, to take another
example of a named entity that is not an object. The reason no
additional rules are needed is that unlike types natures don't have
any operators, in particular no predefined ones. Therefore, nothing
else has to be said about the subject.
b) Mentioning quantities in section 4.3.3.1
All the rules in this section are formulated for objects
characterized by a type. This includes constants, variables,
signals, files, and quantities. The reason why terminals are
mentioned in the last sentence is that terminals do not have types:
they have natures. The sentence says that the same rules apply to
terminals if the appropriate substitutions of nature for type and
subnature for subtype are made.
In summary, both cases are covered by the language of the LRM, in the
first case because according to the definitions an aliase of a nature
is a nonobject alias and there is no exclusion, in the second case
because a quantity is a typed object. These conclusions may be
unexpected, but they are based on the parsimonious style of the LRM.
Thanks.
Ernst Christen
James J Kulikowski writes:
> In reviewing the VHDL-AMS LRM, we noticed that while it is possible to
> alias terminals and quantities, it is not apparent from the LRM (section
> 4.3.3) whether or not it is possible to alias natures. The LRM does
> state: "A nonobject alias is an alias whose alias designator dentoes
> some named entity other than an object.". This would seem to include
> natures. However in section 4.3.3.2 (nonobject aliases) it makes no
> mention of natures. Should a new paragraph be added after paragraph (e)
> that is similar to (e), but devoted to natures rather than types? Was
> this an oversight or is there some reason that aliasing of natures is
> avoided?
> Also, the last sentence of section 4.3.3.1 (object aliases) mentions
> terminals, but shouldn't quantities also be mentioned there?
> --
> Jim Kulikowski (jjk@cadence.com, 630-510-9858)
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