Subject: aliasing natures in VHDL-AMS
From: James J Kulikowski (jjk@cadence.com)
Date: Mon Nov 12 2001 - 12:32:09 PST
In reviewing the VHDL-AMS LRM, we noticed that while it is possible to
alias terminals and quantities, it is not apparent from the LRM (section
4.3.3) whether or not it is possible to alias natures. The LRM does
state: "A nonobject alias is an alias whose alias designator denotes
some named entity other than an object.". This would seem to include
natures. However in section 4.3.3.2 (nonobject aliases) it makes no
mention of natures. Should a new paragraph be added after paragraph (e)
that is similar to (e), but devoted to natures rather than types? Was
this an oversight or is there some reason that aliasing of natures is
avoided?
Also, the last sentence of section 4.3.3.1 (object aliases) mentions
terminals, but shouldn't quantities also be mentioned there?
-- Jim Kulikowski (jjk@cadence.com, 630-510-9858)
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