Subject: Fwd: FDL'01 CFP
From: Alain Vachoux (alain.vachoux@xemics.com)
Date: Thu Dec 14 2000 - 22:59:43 PST
Hello,
FYI.
Alain Vachoux
>Delivered-To: 1076-1@epfl.ch
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>Date: Thu, 14 Dec 2000 14:08:42 +0100
>To: sddl@vhdl.org, hdlcon@vhdl.org, vital@vhdl.org, codesign@vhdl.org,
> ieee-dasc@vhdl.org, 1076-1@epfl.ch, verilog@cds3075.Cadence.COM,
> verilog-a@cds3075.Cadence.COM, mhdl@nosc.mil,
> isss-people@ics.uci.edu,
> codesign@ifi.unizh.ch, sig-vhdl@cefriel.it, arch@ovi.org,
> dcwg@vhdl.org, vlog-synth@eda.org, 1364core@ovi.org, 1364@ovi.org,
> stds-dasc@eda.org, viuf-all@vhdl.org, cenelec-tc217wg2@epfl.ch,
> vhdlpli@vhdl.org
>From: Eugenio Villar <villar@teisa.unican.es>
>Subject: FDL'01 CFP
>
>We apologize if you receive multiple copies:
>
>************************************************************
> ****** *** * * ***** *
> * * * * * * * *
> ** * * * * * *
> * * * * * * *
> * *** ***** ***** *
>************************************************************
> FORUM on DESIGN LANGUAGES
> September 3-7, 2001 - Lyon, France
>************************************************************
>A SIG-VHDL event sponsored by ECSI,
>co-sponsored by IFIP 10.5*, ACM-SIGDA**, ITG**, GMM**
>(*: with no financial participation, **: pending)
>
>************************************************************
> CALL FOR CONTRIBUTIONS
>************************************************************
>www.ecsi.org/ecsi/fdl/fdl01
>
>****************************************************************
> Eugenio Villar
> Microelectronics Engineering Group Tel. +34 942 201398
> E.T.S.I.Industriales y Telecom. Fax. +34 942 201873
> University of Cantabria email. villar@teisa.unican.es
> Avda. Los Castros s/n, 39005 Santander, Spain
>****************************************************************
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