Subject: Definition for matrices in VHDL-AMS
From: Walter Commerell (commerell@fh-ulm.de)
Date: Tue Dec 12 2000 - 00:14:21 PST
Hello,
we're working on a VHDL-AMS compiler to Matlab/Simulink. For this there
are some questions. Can anybody give an answer?
Is VHDL-AMS case sensitive? Where is it in the LRM?
Is there a definition in the actual VHDL-AMS language for matrices to
describe the following example?
How can elements of a matrix accessed?
Example:
END ENTITY StateSpace;
ARCHITECTURE abcd OF StateSpace IS
QUANTITY x: real_vector(a'range(1));
BEGIN
x'dot == a*x + b*u;
y == c*x + d*u;
END ARCHITECTURE abcd;
---------------------------------------------
ENTITY testbench IS
END ENTITY testbench;
ARCHITECTURE statespace OF testbench IS
QUANTITY u: real_vector(1 TO 2);
QUANTITY y: real;
BEGIN
s: ENTITY StateSpace(abcd)
GENERIC MAP (a => ((0.12, 2.0), (3.0, 1.5)),
b => ((2.0, 7.0), (3.0, 1.0)),
c => (0.1, 2.0),
d => (0 TO 1 => 0.0))
PORT MAP (u => u, y => y);
u == (now, sin(now));
END ARCHITECTURE statespace;
With regards
Walter Commerell
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