Subject: Request for Q'Above(E) clarification
From: Tim McBrayer (tmcbraye@mailhost.viewlogic.com)
Date: Mon Sep 25 2000 - 10:41:15 PDT
Please forgive me if this appears on the VHDL-AMS mailing list twice: I
sent this some time back and it apparently never made it to the list.
To the VHDL-AMS 1076.1 Working Group:
My colleagues and I have been having a disagreement over the precise
definition of the implicit signal Q'above(E) in VHDL-AMS. I was hoping
that we could receive some clarification on this matter. Here are the two
interpretations.
Interpretation A:
This interpretation follows a strict, LRM-based understanding. Each
textual occurrence of the form Q'Above(E) causes the instantiation of one
implicit signal.
In this interpretation, all implicit signals Q'Above(E) are unresolved,
and thus have only one driver, which is assigned to solely by the analog
solver. When the value of Q'Above(E) is read in a process body, the value
of the implicit signal is read. No attempt is made to evaluate E or
compare it to the value of Q.
This interpretation leads to potentially misleading VHDL code. Take the
following code fragment. In it, assume Q is 1.0, E is 0.0, and Q'Above(E)
is TRUE when the wait statement resumes.
misleading: process
variable E: real := 0.0;
variable B: boolean := FALSE;
begin
<...>
wait for 100 ns;
E := 2.0;
B := Q'Above(E);
<...>
end process misleading;
In this interpretation, the boolean variable B will be assigned the value
of TRUE, as this is the value stored in the implicit signal Q'Above(E).
Note, however, that when the assignment to B is executed, Q is not
actually "Above E"; that is, Q < E during the assignment to B. This is
the source of the difference of opinion.
Interpretation B:
This interpretation is very similar in that it too implements one signal
for each textual occurrence of the form Q'Above(E), as a single-driver,
unresolved signal. The difference comes when the value of this signal is
read.
At process execution time, instead of reading the value of the implicit
signal Q'Above(E) as stored in the kernel, the boolean value (Q > E) is
recomputed upon execution of the relevant code. This will take into
account any changes to values used in the computation of the value of the
expression E. With the example above, this interpretation will recompute
(Q > E) with quantity Q = 1.0 and variable E = 2.0 . With these values,
(Q > E) is FALSE, so the assignment to B will cause B to have the value
FALSE.
This interpretation has the benefit that the sequential statement:
B := Q'Above(E);
does what seems logical; that is, at the moment of execution, B is
assigned (Q > E). However, is does not adhere to strict VHDL signal
semantics. The value of the implicit signal becomes more or less
unused, and the signal is only used for event information, triggering
wait statement resumption and such.
The question, of course, is which interpretation is correct according to
the intent of the 1076.1 LRM. Thank you for considering this matter.
Best regards,
-- Tim McBrayer (508) 303-5333 Principal Software Engineer e-mail me for my PGP key Innoveda Inc. tmcbrayer@innoveda.com
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