UpdateStdLogicArith < P1076

P1076 Web>Vhdl2019CollectedRequirements>UpdateStdLogicArith (2020-02-17, JimLewis) (raw view)EditAttach
---+ Update std_logic_arith

%TOC%

---++ Proposal Editing Information
   * Who Updates: OPEN, Main.JimLewis
   * Date Proposed: 2012-08-17
   * Date Last Updated: 2012-08-17
   * Priority:
   * Complexity:
   * Focus: Testbench
---++ Summary

Update std_logic_arith to simplify interfacing with numeric_std

Suggested during [[MeetingFebruary16][February 16, 2012]]

   * First step, propose change to vendor owner.
   * If that does not take, propose adoption by IEEE
   * Propose that it is donated to IEEE or alternately propose that vendor makes a change

---++ Related and/or Competing Issues: No

---++ Proposal
---+++ Proposal Part 1: Alias types unsigned and signed to numeric_std

Purpose: Simplify interfacing between designs using std_logic_arith and numeric_std.

Change the definition of std_logic_arith.unsigned and std_logic_arith.signed to:
<verbatim>alias unsigned is numeric_std.unsigned ; 
alias signed is numeric_std.signed ;</verbatim>

---+++ Proposal Part 2: Alias all common subprograms

<pre>Pro: Simplify transition to numeric_std 
Con: Behavior is slightly different. 
       Particularly wrt warnings vs errors. 
       Probably too much.</pre>

---++ Questions

---++ General Comments

Why bother? Both of the packages have been around for 20+ years and they both work how they work. Part 2 of the proposal indicates that it will break existing code in certain situations. The benefit listed on this proposal is to "Simplify interfacing between designs using std_logic_arith and numeric_std" but no actual examples of such simplifications are provided. -- Main.KevinJennings - 2014-12-08
---++ Supporters

_Add your signature here to indicate your support for the proposal_

_-- Main.JimLewis - 2014-12-04_
Topic revision: r4 - 2020-02-17 - 15:34:44 - JimLewis
P1076