(r25) UCMinimalRTLSignalInterface < P1076

P1076 Web>Vhdl2019CollectedRequirements>InterfaceAndBundleEnhancements>UCMinimalRTLSignalInterface (revision 25) (raw view)~~EditAttach~~
---+ Minimal RTL Record Based Interface Use Case

%TOC%

---++ Assumptions

   * This use case is intended to propose a minimal implementation of an enhanced interface support for RTL use based on the standard *record* type.
   * Existing designs can use *record* types to encapsulate an interface, but propagating a *record* through a *port* (or *parameter*) structure limits the *record* signal to a common mode for all of its elements. %BR% This can be overcome by changing the *port* mode to *inout* and ensuring that all *record* elements are of a resolved type. %BR% However this could be viewed as ignoring the mode concept and in many companies (especially designing with FPGAs) it would break coding guidelines (example rule: "do not use resolved types within core designs").
   * This use case proposes a new construct for named directional mode control on *entity/function/procedure* declarations. %BR% Various proposals have suggested the following options: 
      * *port* *configuration* 
         * advantage? uses existing VHDL keywords
         * disadvantage? too verbose
         * disadvantage? suggests *entity* only use
      * *modport* 
         * advantage? meaning generally understood
         * disadvantage? too Verilog'ish
      * *view* 
         * advantage? concise
         * advantage? use as *record* *view*
         * advantage? extensible to *array* *view* and *bundle* *view*
         * disadvantage? new VHDL keyword
   * This use case proposes using a new *view* keyword to describe a new VHDL construct in order to hierarchically control modes for each element of a composite type when used in an *entity* or subprogram interface structure (termed in BNF definitions as an "interface_object_declaration").
   * Objects associated with a composite *type* will need to allow elements of said composite *type* to be driven independently from the object as a whole (e.g. a *signal*).

---++ Use Case Example

   * A simple parallel data interface with an assumed protocol (not defined here).

---+++ The Package

   * In order to make declarations visible across hierarchies, they are defined within a *package*:

<sticky><pre>
   <B>package</B> if_pkg
      <B>generic</B>(
         dwidth_jg <B>: positive</B>
      );
      <B>is</B>
      <B>constant</B> dwidth_jc  <B> : positive</B> := dwidth_jg;
      <B>subtype</B>  dwidth_jrt <B>is natural range</B> dwidth_jc - 1 <B>downto</B> 0;
      <B>subtype</B>  data_vst   <B>is std_logic_vector</B>(dwidth_jrt);
</pre></sticky>

   * Define the record type and include generically controlled data width.

<img width="550" alt="" src="%ATTACHURLPATH%/UC_BAH_RecordStructure.png" height="200" />

<sticky><pre>
      <B>type</B> if_bus_r <B>is record</B>
         enbl_e  <B>: std_logic</B>;
         strt_e  <B>: std_logic</B>;
         data_ve <B>: std_logic_vector</B>(dwidth_jrt);
         ack_e   <B>: std_logic</B>;
         err_e   <B>: std_logic</B>;
      <B>end record</B> if_bus_r;
</pre></sticky>

   * Use a new *record* *view* construct to specify a hierarchical named mode view of this record type at the transmitter.

<sticky><pre>
      <B>record view</B> if_bus_tx_rvw <B>of</B> if_bus_r <B>is</B>
         enbl_e  <B>: out std_logic</B>;
         strt_e  <B>: out std_logic</B>;
         data_ve <B>: out std_logic_vector</B>(dwidth_jrt);
         ack_e   <B>: in  std_logic</B>;
         err_e   <B>: in  std_logic</B>;
      <B>end record view</B> if_bus_tx_rvw;
</pre></sticky>

   * Use a new attribute to specify the opposite hierarchical named mode view of this record type at the receiver. %BR% Use the *converse* attribute to reverse the mode directions.

<sticky><pre>
      <B>record view</B> if_bus_rx_rvw <B>of</B> if_bus_r <B>is</B>
         if_bus_tx_rvw'<B>converse</B>;
      <B>end record view</B> if_bus_rx_rvw;
</pre></sticky>

   * Use a new attribute to specify a named mode view of this record type at the monitoring point. %BR% Use the *monitor* attribute to set all mode directions to 'in'.
<sticky><pre>
      <B>record view</B> if_bus_chk_rvw <B>of</B> if_bus_r <B>is</B>
         if_bus_tx_rvw'<B>monitor</B>;
      <B>end record view</B> if_bus_chk_rvw;

   <B>end package</B> if_pkg;
</pre></sticky>

---

The new attribute value equivalent mode views are shown below:

   * The *converse* *record* *view* 'if_bus_rx_rvw' is equivalent to:
<sticky><pre>
      <B>record view</B> if_bus_rx_rvw <B>of</B> if_bus_r <B>is</B>
         enbl_e  <B>: in  std_logic</B>;
         strt_e  <B>: in  std_logic</B>;
         data_ve <B>: in  std_logic_vector</B>(dwidth_jrt);
         ack_e   <B>: out std_logic</B>;
         err_e   <B>: out std_logic</B>;
      <B>end record view</B> if_bus_rx_rvw;
</pre></sticky>

   * The *monitor* *record* *view* 'if_bus_chk_rvw' is equivalent to:
<sticky><pre>
      <B>record view</B> if_bus_chk_rvw <B>of</B> if_bus_r <B>is</B>
         enbl_e  <B>: in  std_logic</B>;
         strt_e  <B>: in  std_logic</B>;
         data_ve <B>: in  std_logic_vector</B>(dwidth_jrt);
         ack_e   <B>: in  std_logic</B>;
         err_e   <B>: in  std_logic</B>;
      <B>end record view</B> if_bus_chk_rvw;
</pre></sticky>

---++ The Structural Interconnect Level

The structural interconnect now becomes almost trivial, but that is the intent:

   * Instantiate the interface package and *use* it.
   * This creates an 8 bit data bus version of the record.

<img width="550" alt="" src="%ATTACHURLPATH%/UC_BAH_RecordStructure8.png" height="200" />

<sticky><pre>
   <B>package</B> if_8_pkg <B>is new</B> if_pkg
      <B>generic map</B>(
         dwidth_jg => 8
      );
   <B>use</B> work.if_8_pkg<B>.all</B>;
</pre></sticky>

   * Declare a trivial test bench top entity:

<img width="550" alt="" src="%ATTACHURLPATH%/UC_BAH_RecordInterfaceTop.png" height="300" />

<sticky><pre>
   <B>entity</B> if_tb_ent <B>is</B>
   <B>end entity</B> if_tb_ent;
</pre></sticky>

   * Define the test bench *architecture* and declare the necessary signals:

<sticky><pre>
   <B>architecture</B> RecordInterfaceTop <B>of</B> if_tb_ent <B>is</B>
      <B>signal</B> rst_s     <B>: std_logic</B>;
      <B>signal</B> clk_s     <B>: std_logic</B>;
      <B>signal</B> if_bus_rs <B>:</B> if_8_pkg.if_bus_r;
</pre></sticky>

   * Declare the monitor *procedure*:

<img width="550" alt="" src="%ATTACHURLPATH%/UC_BAH_MonitorInterface.png" height="300" />

<sticky><pre>
      <B>procedure</B> monitor_prcd(
            <B>signal</B> rst_si      <B>: in   std_logic</B>;
            <B>signal</B> clk_si      <B>: in   std_logic</B>;
            <B>signal</B> if_bus_rsif <B>: view</B> if_8_pkg.if_bus_chk_rvw
         ) <B>is</B>
      <B>begin</B>
         ...
      <B>end procedure</B> monitor_prcd;
</pre></sticky>

   * Instantiate the transmitter

<sticky><pre>
   begin
      transmit_inst <B>: component</B> transmit_cmp
         <B>port map</B>(
            rst_i          => rst_s,
            clk_i          => clk_s,
            if_bus_tx_rif  => if_bus_rs 
         );
</pre></sticky>

   * Instantiate the receiver

<sticky><pre>
      receive_inst <B>: component</B> receive_cmp
         <B>port map</B>(
            rst_i          => rst_s,
            clk_i          => clk_s,
            if_bus_tx_rif  => if_bus_rs 
         );
</pre></sticky>

   * Instantiate the monitor

<sticky><pre>
      monitor_inst <B>:</B> monitor_prcd(rst_s, clk_s, if_bus_rs);

   <B>end architecture</B> RecordInterfaceTop;
</pre></sticky>

---++ The Entities

---+++ The Transmitter

   * First '*use*' the 8 bit interface *package*

<sticky><pre>
   <B>use</B> work.if_8_pkg.<B>all</B>;
</pre></sticky>

   * The transmitter *entity*. %BR% N.B. It does not need a generic declaration for the data bus width as that is defined within the package. %BR% The new *view* keyword is now used to specify a new mode. It indicates that it wil be followed by the hierarchical mode and in this case that is defined using the named *record* *view* declared in the interface package for the transmitter terminus of the interface:

<img width="550" alt="" src="%ATTACHURLPATH%/UC_BAH_TransmitterInterface.png" height="300" />

<sticky><pre>
   <B>entity</B> transmit_ent <B>is</B>
      <B>port(</B>
         rst_i         <B>: in   std_logic</B>;
         clk_i         <B>: in   std_logic</B>;
         if_bus_tx_rif <B>: view </B>if_8_pkg.if_bus_tx_rvw 
      );
   <B>end entity</B> transmit_ent;
</pre></sticky>

   * Declare the internal signals.

<sticky><pre>
   <B>architectur</B>e rtl <B>of</B> transmit_ent <B>is</B>
         <B>signal</B> enbl_s  <B>: std_logic</B>;
         <B>signal</B> strt_s  <B>: std_logic</B>;
         <B>signal</B> data_vs <B>: std_logic_vector</B>(if_8_pkg.dwidth_jrt);
         <B>signal</B> ack_s   <B>: std_logic</B>;
         <B>signal</B> err_s   <B>: std_logic</B>;
   <B>begin</B>
</pre></sticky>

   * Compose/decompose the interface record: 
      * Transmit the data with the enable and start control signals.
      * Receive the acknowledge and error status signals.

<sticky><pre>
      if_bus_tx_rif.enbl_e  <= enbl_s;
      if_bus_tx_rif.strt_e  <= strt_s;
      if_bus_tx_rif.data_ve <= data_vs ;

      ack_s <= if_bus_tx_rif.ack_e;
      err_s <= if_bus_tx_rif.err_e;

   <B>end architecture</B> rtl;
</pre></sticky>

---+++ The Receiver

   * First '*use*' the 8 bit interface *package*

<sticky><pre>
   <B>use</B> work.if_8_pkg<B>.all</B>;
</pre></sticky>

   * The receiver *entity* %BR% N.B. This also does not need a generic declaration for the data bus width as it is defined within the package:

<img width="550" alt="" src="%ATTACHURLPATH%/UC_BAH_ReceiverInterface.png" height="300" />

<sticky><pre>
   <B>entity</B> receive_ent <B>is</B>
      <B>port</B>(
         rst_i         <B>: in   std_logic</B>;
         clk_i         <B>: in   std_logic</B>;
         if_bus_rx_rif <B>: view</B> if_8_pkg.if_bus_rx_rvw 
      );
   <B>end entity</B> receive_ent;
</pre></sticky>

   * Declare the internal signals.

<sticky><pre>
   <B>architecture</B> rtl <B>of</B> transmit_ent <B>is</B>
         <B>signal</B> enbl_s  <B>: std_logic</B>;
         <B>signal</B> strt_s  <B>: std_logic</B>;
         <B>signal</B> data_vs <B>:</B> if_8_pkg.data_vst;
         <B>signal</B> ack_s   <B>: std_logic</B>;
         <B>signal</B> err_s   <B>: std_logic</B>;
   <B>begin</B>
</pre></sticky>

   * Compose/decompose the interface record: 
      * Receive the data with the enable and start control signals.
      * Return the acknowledge and error status signals.

<sticky><pre>
      enbl_s  <= if_bus_rx_rif.enbl_e;
      strt_s  <= if_bus_rx_rif.strt_e;
      data_vs <= if_bus_rx_rif.data_ve;

      if_bus_rx_rif.ack_e <= ack_s;
      if_bus_rx_rif.err_e <= err_s;

   <B>end architecture</B> rtl;
</pre></sticky>

---++ Conclusions

   * The main additions to the language are used to provide enhanced mode control at *entity*, *function* and *procedure* interfaces.
   * This is achieved using a new *view* reserved keyword.
   * The *view* keyword is used to declare named hierarchical interface mode views for composite types.
   * The composite type views can be defined as a named *record* *view* or a named *array* *view*, for example:
<sticky><pre>
      <B>record view</B> if_bus_tx_rvw <B>of</B> if_bus_r <B>is</B>
         enbl_e  <B>: out std_logic</B>;
         strt_e  <B>: out std_logic</B>;
         data_ve <B>: out std_logic_vector</B>(dwidth_jrt);
         ack_e   <B>: in  std_logic</B>;
         err_e   <B>: in  std_logic</B>;
      <B>end record view</B> if_bus_tx_rvw;
</pre></sticky>
   * These named views are then associated with elements in an interface list using the new *view* keyword as a mode indicator to identify the named mode view and associate it with a *constant*, *signal* or *variable* object, for example:
<sticky><pre>
         rst_i         <B>: in   std_logic</B>;
         clk_i         <B>: in   std_logic</B>;
         if_bus_rx_rif <B>: view</B> if_8_pkg.if_bus_rx_rvw
</pre></sticky>
   * Additionally, two new attributes are proposed, namely *converse* and *monitor*, which are used with named mode views to provide inverted *in/out* and all *in* mode views respectively, for example: %BR% (Refer to proposal: [[P1076.InterfaceAttributes][Interfaces: Attributes for Interfaces]])
<sticky><pre>
      <B>record view</B> if_bus_rx_rvw <B>of</B> if_bus_r <B>is</B>
         if_bus_tx_rvw'converse;
      <B>end record view</B> if_bus_rx_rvw;
</pre></sticky>
   * The *monitor* attribute generating an all *in* *record* *view* or *array* *view* is essentially redundant. %BR% A connection object with a composite type can be passed through an entity object interface using the *in* mode operating on the complete composite type.
   * The *converse* attribute generating opposite modes would need a parameter to be able to select between an *out* port transformation or a *buffer* port transformation : 
      * *out* ports selected: 
         * *in* mode transforms to *out* mode
         * *out* mode transforms to *in* mode
         * *buffer* mode transforms to *in* mode
      * *buffer* ports selected: 
         * *in* mode transforms to *buffer* mode
         * *buffer* mode transforms to *in* mode
         * *out* mode transforms to *in* mode
      * *inout* modes are not transformed in either port selections, they remain as *inout* modes.
      * Refer to proposal: [[P1076.InterfaceAttributes][Interfaces: Attributes for Interfaces]]
   * Connection objects associated with composite types are in effect composite objects. %BR% This new hierarchical *view* mode will require that each element of a composite type be capable of being driven indepentently from the object as a whole, i.e. as if it were a composite object. %BR% This is a new requirement for the composite type, i.e. not just at the interface termini where the *view* mode dictates the driving or reading of the individual element, but also on the connection object (e.g. *signal*) which has no association with a mode, just with the composite type.
   * Events may still be generated on the object as a whole, but may benefit from being associated individually with the composite type elements. %BR% This would give the enhanced ability of being able to use indivdual elements of a composite type within sensitivity lists.
   * The ability to introspcetively analyse records, specifically to be able to loop through element names of a record. %BR% Refer to proposals: 
      * [[P1076.RecordIntrospection][Record Introspection]]
      * [[P1076.RecordMemberAttribute][Record Introspection & Indexing]]
Attachments
I	Attachment	Action	Size	Date	Who	Comment
png	UC_BAH_MonitorInterface.png	manage	40.2 K	2015-08-06 - 17:06	BrentHahoe	RTL monitor interface.
png	UC_BAH_ReceiverInterface.png	manage	38.1 K	2015-08-06 - 17:01	BrentHahoe	RTL receiver interface.
png	UC_BAH_RecordInterfaceTop.png	manage	27.0 K	2015-08-06 - 17:02	BrentHahoe	RTL record based interface use case.
png	UC_BAH_RecordStructure.png	manage	28.3 K	2015-08-06 - 17:03	BrentHahoe	RTL record structure.
png	UC_BAH_RecordStructure8.png	manage	28.4 K	2015-08-06 - 17:04	BrentHahoe	RTL record structure (8 bit).
png	UC_BAH_TransmitterInterface.png	manage	37.4 K	2015-08-06 - 17:05	BrentHahoe	RTL transmitter interface.
Topic revision: r1 - 2016-01-21 - 11:52:52 - TWikiGuest
P1076