P1076 Web>VHDLProposals>DerivedEnumerationTypes (2017-04-02, PatrickLehmann)EditAttach

Derived Enumeration Types

Proposal Details

Authors	Patrick Lehmann
Date Proposed	2017-04-03
Last Updated	2017-04-03
Focus	simulation and synthesis
LCS	TBD

Summary
Current Situation
Requirement
Use Cases
Implementation details
Code Examples
Arguments FOR
Arguments AGAINST
General Comments
Supporters

Summary

VHDL Libraries and frameworks like PoC or UVVM like to specify a minimum set of enumeration literals for different purposes. The user shall then be enabled to extend such a basic enumeration type with his own user defined enumeration literals, without using copy and past to create such a list. It's preferred to find and define a semantic (derived relationship, subtype relationship) between the base and derive type.

Current Situation

Currently, enumeration literals can not be shared between different enumeration types. If a library provider allows a user to create a user defined enumeration type, then he can only specify the minimum content of such a type by coding guide lines and/or a template.

Requirement

Features:

Append literals
Implicitly created conversion functions

Use Cases

Add some use cases.

Implementation details

How is it implemented?

Code Examples

type BaseEnum is (
  STATUS_IDLE,
  STATUS_RESETING,
  STATUS_ERROR
);

type myStatus is new BaseEnum (
  STATUS_READING,
  STATUS_READING_COMPLETE,
  STATUS_WRITING,
  STATUS_WRITING_COMPLETE
);
--type myStatus is new BaseEnum (
--  STATUS_IDLE,
--  STATUS_RESETING,
--  STATUS_ERROR
-- append new literals
--  STATUS_READING,
--  STATUS_READING_COMPLETE,
--  STATUS_WRITING,
--  STATUS_WRITING_COMPLETE
--);

Arguments FOR

Arguments AGAINST

General Comments

Supporters

Patrick Lehmann - 2017-04-03
Add your signature here to indicate your support for the proposal

Topic revision: r1 - 2017-04-02 - 22:25:12 - PatrickLehmann

P1076