ConfigureDirectInstantiation < P1076

P1076 Web>Vhdl2019CollectedRequirements>ConfigureDirectInstantiation (2020-11-25, JimLewis) (raw view)EditAttach
---+ Configure Direct Instantiation

IN PROGRESS!

%TOC%

---++ Proposal Information
   * Current Owner: Main.RyanHinton
   * Contributors: Main.RyanHinton, Main.JimLewis, Main.AndyJones, Main.DanielKho
   * Date Proposed: 2013-Dec-12
   * Date Last Updated: 2014-Jan-14
   * Priority:
   * Complexity:
   * Focus: Productivity enhancement
   * Related Issues: None
   * Competing Issues: None

---++ Requirement Summary

Provide a method to specify what architecture(s) should be used in direct instantiations one or more levels of hierarchy below the current.

---++ Rationale

Direct instantiation is highly convenient for the majority of VHDL design. (Whether or not you like it, your coworker or third-party designer may.) Direct instantiation provides an opportunity to specify an architecture at the point of instantiation. Otherwise, the default architecture (last analyzed) will be elaborated. When a direct instantiation does not specify an architecture, it is desirable to be able to specify the architecture similar to a configuration.

---++ Proposal 1: Configuration Specification

WRITE ME!

This direct instantiation config spec goes in the declarative region of the architecture where the instance appears. The syntax essentially requires that.

Main.JimLewis: It would be interesting to see an example of this as I have always viewed direct instantiation as subsuming the capability of a component delcaration, component instance, and a configuration specification. As a result, I only need the configuration declaration.
---++ Proposal 2: Configuration Declaration

Designers who use direct instantiation will probably prefer to use configuration specifications. But if it's your coworker who likes them, then the analogous changes to configuration declarations should apply equally as well.

&lt;copied (and adapted) from email reflector&gt;:

*Top-level design: block0.vhdl*

<verbatim>library ieee,work; ...
use work.subblock0;

entity block0 is port(...);
end entity block0;

architecture structural of block0 is begin
    instance0: entity work.subblock0 port map(...);
end architecture structural;</verbatim>

<br /><strong>Sub-level design: subblock0.vhdl, subblock0_arch.vhdl</strong><br />The entity of subblock0 is specified in subblock0.vhdl.<br />The architecture of subblock0 is specified in subblock0_arch.vhdl.<br /><br /><strong>cfg_block0.vhdl</strong>

<verbatim>library work;
use work.subblock0;

configuration cfg_block0 of block0 is
    for structural
        for sub0_arch0: subblock0
            use entity work.subblock0(arch0);
        end for;
    end for;
end configuration cfg_block0;</verbatim>

---++ Proposal 3: Make component declarations Trivial
Alternatives:

<verbatim>
component Fred is entity work.Freddy ; 
alias Fred is work.freddy'component ; 
work.Fred'component ;
</verbatim>

What about library references and use clauses associated with Fred?
1. Do we import them implicitly.
2. Must write them separately.



---++ Comments
---+++ General

---+++ Arguments Against

---++ Supporters

-- Main.RyanHinton - 2014-01-15

-- Main.JimLewis - 2014-12-04

-- Main.DanielKho - 2015-01-01
Topic revision: r7 - 2020-11-25 - 23:32:41 - JimLewis
P1076