(r1) ClocksOrdering < P1076

P1076 Web>Vhdl2019CollectedRequirements>ClocksOrdering (revision 1) (raw view)~~EditAttach~~
---+ Zero delay ordering of Clocks vs. Data signals

%TOC%
---++ Recommendation: Reject

---++ Proposal Information
   * Who Updates:
   * Date Last Updated
   * Priority:
   * Complexity:
   * Focus: Performance

---++ Requirement Summary & Rationale

[[http://www.eda.org/vhdl-200x/vhdl-200x-perf/proposals/perf07.txt"][Performance proposal here]]

[[PreponedProcess][See Preponed Process Proposal]]

---++ Arguments For

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---++ Arguments Against

_Add your signature here to indicate your do not support for the proposal_

---++ General Comments
---+++ Email Reflector Comments

   * [[http://www.eda.org/vhdl-200x/vhdl-200x-perf/hm/][Original VHDL-200X Simulation Performance Reflector Archive]]

---++++ From: [[Main.PeterFlake][Peter Flake]] (Thu Jan 03 2013 - 09:48:21 PST)

Perf 7: Zero-delay ordering of signals

It is unclear what algorithm is required here. It must cope with multiple clock domains and asynchronous circuits.

---++++ From: [[Main.BrentHahoe][Brent Hayhoe]] (Mon Jan 21 2013 - 13:09:26 PST)

PERF-07 Zero-delay ordering of signals

I am presuming that this is to do with clock edges arriving too late (in terms of deltas) with respect to data.

Due to zero delay buffers in the gate level design, they can arrive after the data (from the test bench) rather than just before.

It is an inconvenience, but something which can be worked around. I just add a delta delay loop on the clock in the test bench, which adds as many delta delay cycles to the clock as is required to match the delay in the design.

Having said this, I haven't come across this problem for along time, but then again I don't do many zero delay gate-level simulations either.

<sticky>
<pre>
<verbatim>
My example:

      ---------------------------------------------------------
     |
     | Test Bench          ------------------------------------
     |                    |
     |   CLK              |    |\     |\     |\     |\
     | --->------ ----->--|----| >----| >----| >----| >---
     |           |        |    |/     |/     |/     |/    |
     |        -------     |                               |
     |       | delta |    |     ------<-------------<-----
     |       | delay |    |    |
     |       |  loop |    |    v
     |        -------     |    |          Gate-Level Design
     |           |        |    |
     |          -v-       |   -v-
     |  DATA   |   |      |  |   |
     | --->----|   |--->--|--|   |-------
     |         |   |      |  |   |
     |          ---       |   ---
     |                    |

Where the 'delta delay loop' code is something like:

    signal clk_vs : Std_Logic_Vector(MAX_jg - 1 downto 0);
  begin
    clk_vs(0) <= clk_i;
    for I_jlv 0 to MAX_jg - 2
      loop
      clk_vs(I_jlv + 1) <= clk_vs(I_jlv);
    end loop
    clk_b <= clk_vs(MAX_jg);
</verbatim>
</pre></sticky>
Topic revision: r1 - 2020-02-17 - 15:34:28 - TWikiGuest
P1076