Repair Example in Section 14.2

Proposal Details

• Language Version: VHDL-2008
• Classification: LRM Correction
• Summary: One of the examples in LRM section 14.2 is incorrect.
• Relevant_LRM_Sections: 14.2
• Authors_Name: CliffordWalinsky
• Authors_Fax_Number: 503-685-0892
• Authors_Email_Address: cliffw@modelNOSPAM.com
• Authors_Affiliation: Mentor Graphics
• Authors_Address1: 8005 SW Boeckman Rd.
• Authors_Address2: Wilsonville, OR 97070
• Authors_Address3:

• Date Submitted:September 12, 2013
• Date Analyzed:
• Author of Analysis:
• Revision Number: 1
• Date Last Revised: September 12, 2013

Description of Problem

In section 14.2 of the language standard, "Elaboration of a design hierarchy", there is an extended example demonstrating both legal and illegal external references. Legal external references are those in which the target of the reference has been elaborated before the reference itself is elaborated. The example contains an error.

The example contains the following declarations:

alias DONE_SIG is <<signal .TOP.DUT.DONE: BIT>>; -- Legal
constant DATA_WIDTH: INTEGER := << signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH;
-- Illegal, because .TOP.DUT.DATA has not yet been elaborated
-- when the expression is evaluated

The DONE_SIG declaration is illegal. As the comment below the DATA_WIDTH declaration explains, .TOP.DUT.DATA has not yet been elaborated; hence, .TOP.DUT.DONE cannot have been elaborated at this point.

Proposed Resolution

The declarations should be replaced with the following:

alias DONE_SIG is <<signal .TOP.DUT.DONE: BIT>>; -- Illegal, see below
constant DATA_WIDTH: INTEGER := << signal .TOP.DUT.DATA: BIT_VECTOR>>'LENGTH;
-- Illegal, because .TOP.DUT has not yet been elaborated
-- when the expression is evaluated 

VASG-ISAC Analysis & Rationale

VASG-ISAC Recommendation for IEEE Std 1076-2008

VASG-ISAC Recommendation for Future Revisions

Supporters

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CliffordWalinsky