2021_0304_Meeting < P1076

P1076 Web>Vhdl202X_MeetingMinutes>2021_0304_Meeting (2021-03-06, UnaiCorral) (raw view)EditAttach

---+ P1076 Minutes from March 4, 2021
---++ Attendees
   * Peter Flake, Unai Martinez-Corral, Marlon James, Pablo, Jim Lewis
---++ Meeting Discussion
   * VHPI
      * The callback reason vhpiCbPLIError is only defined in header <code>vhpi_user.h</code> (annex) but not in the LRM itself. There might be other similar inconsistencies.
         * [[https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/47]]
      * Is it possible for the body of a VHPI callback to trigger another callback before returning control to the simulator?
         * https://github.com/cocotb/cocotb/issues/2178
         * This can happen in Verilog, because signals are updated instantly. However, it should not be possible in VHDL, where signals are updated after the subprogram returns. Anyway, it should be clarified in the LRM.
      * Jim will try to reach some of the people that worked on including VHPI in the standard, back in 2005-2008.
   * DPI
      * We discussed about the conception of "reachable" for allowing a subprogram to be exported. The most direct interpretation is to constraint exports to items reachable through external names, according to the language's rules. However, simulators/tools can uniquely reach other subprograms, such as the ones defined in anonymous processes, in architectures, entities, etc. Therefore, all those are also reachable for an implementer.
      * Peter and Unai coordinating on header dev on GitLab /GitHub

---++ Next Meeting
   * March 18th at 11 am

Topic revision: r3 - 2021-03-06 - 17:44:51 - UnaiCorral

P1076